EP2A15 Datasheet, PDF (54/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Figure 32. True-LVDS Receiver Diagram Notes (1), (2)
Receiver
+
Channel
–
RX_CLK1 (3)
×W
Receiver
PLL1
×
W
J
Receiver
+
Channel
–
Receiver Channel 1
Receiver Channel 2
J Bits Wide
Deserializer
Data to
LEs
Receiver
+
Channel
–
Receiver Channel 18
To Global
Clock
Notes to Figure 32:
(1) Two sets of 18 receiver channels are located in each APEX II device. Each set of 18 channels has one receiver PLL.
(2) W = 1, 2, 4 to 10
J = 1, 2, 4 to 10
W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, DDR I/O registers are used.
(3) These clock pins drive receiver PLLs only. They do not drive directly to the logic array. However, the receiver PLL
can drive the logic array via a global clock line.
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Altera Corporation