EP2A15 Datasheet, PDF (15/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Cascade Chain
With the cascade chain, the APEX II architecture can implement functions
with a very wide fan-in. Adjacent LUTs can compute portions of a
function in parallel; the cascade chain serially connects the intermediate
values. The cascade chain can use a logical AND or logical OR (via
DeMorgan’s inversion) to connect the outputs of adjacent LEs. Each
additional LE provides four more inputs to the effective width of a
function, with a short cascade delay. The Quartus II Compiler can create
cascade chain logic automatically during the design process, or the
designer can create it manually during design entry.
Cascade chains longer than 10 LEs are implemented automatically by
linking LABs together. For enhanced fitting, a long cascade chain skips
alternate LABs in a MegaLAB structure. A cascade chain longer than one
LAB skips either from an even-numbered LAB to the next even-numbered
LAB, or from an odd-numbered LAB to the next odd-numbered LAB. For
example, the last LE of the first LAB in the upper-left MegaLAB structure
carries to the first LE of the third LAB in the MegaLAB structure. Figure 7
shows how the cascade function can connect adjacent LEs to form
functions with a wide fan-in.
Figure 7. APEX II Cascade Chain
AND Cascade Chain
OR Cascade Chain
d[3..0]
LUT
d[3..0]
LUT
LE1
LE1
d[7..4]
LUT
d[7..4]
LUT
LE2
LE2
d[(4n — 1)..(4n — 4)]
LUT
d[(4n — 1)..(4n — 4)]
LUT
LEn
LEn
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