EP2A15 Datasheet, PDF (82/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Table 48. APEX II f_MAX ESB Timing Parameters
Symbol
t_ESBARC
t_ESBSRC
t_ESBAWC
t_ESBSWC
t_ESBWASU
t_ESBWAH
t_ESBWDSU
t_ESBWDH
t_ESBRASU
t_ESBRAH
t_ESBWESU
t_ESBDATASU
t_ESBWADDRSU
t_ESBRADDRSU
t_ESBDATACO1
t_ESBDATACO2
t_ESBDD
t_PD
t_PTERMSU
t_PTERMCO
Parameter
ESB asynchronous read cycle time
ESB synchronous read cycle time
ESB asynchronous write cycle time
ESB synchronous write cycle time
ESB write address setup time with respect to WE
ESB write address hold time with respect to WE
ESB data setup time with respect to WE
ESB data hold time with respect to WE
ESB read address setup time with respect to RE
ESB read address hold time with respect to RE
ESB WE setup time before clock when using input register
ESB data setup time before clock when using input register
ESB write address setup time before clock when using input registers
ESB read address setup time before clock when using input registers
ESB clock-to-output delay when using output registers
ESB clock-to-output delay without output registers
ESB data-in to data-out delay for RAM mode
ESB macrocell input to non-registered output
ESB macrocell register setup time before clock
ESB macrocell register clock-to-output delay
Figure shows the dual-port RAM timing microparameter waveform.
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