EP2A15 Datasheet, PDF (5/99 Pages) Altera Corporation – Programmable Logic Device Family

General
Description
APEX II Programmable Logic Device Family Data Sheet
APEX II devices integrate high-speed differential I/O support using the
True-LVDS interface. The dedicated serializer, deserializer, and CDS
circuitry in the True-LVDS interface support the LVDS, LVPECL,
HyperTransport, and PCML I/O standards. Flexible-LVDS pins located
in regular user I/O banks offer additional differential support, increasing
the total device bandwidth. This circuitry, together with enhanced IOEs
and support for numerous I/O standards, allows APEX II devices to meet
high-speed interface requirements.
APEX II devices also include other high-performance features such as
bidirectional dual-port RAM, CAM, general-purpose PLLs, and
numerous global clocks.
Configuration
The logic, circuitry, and interconnects in the APEX II architecture are
configured with CMOS SRAM elements. APEX II devices are
reconfigurable and are 100% tested prior to shipment. As a result, test
vectors do not have to be generated for fault coverage. Instead, the
designer can focus on simulation and design verification. In addition, the
designer does not need to manage inventories of different ASIC designs;
APEX II devices can be configured on the board for the specific
functionality required.
APEX II devices are configured at system power-up with data either
stored in an Altera configuration device or provided by a system
controller. Altera offers in-system programmability (ISP)-capable
configuration devices, which configure APEX II devices via a serial data
stream. The enhanced configuration devices can configure any APEX II
device in under 100 ms. Moreover, APEX II devices contain an optimized
interface that permits microprocessors to configure APEX II devices
serially or in parallel, synchronously or asynchronously. This interface
also enables microprocessors to treat APEX II devices as memory and to
configure the device by writing to a virtual memory location, simplifying
reconfiguration.
APEX II devices also support a new byte-wide, synchronous
configuration scheme at speeds of up to 66 MHz using EPC16
configuration devices or a microprocessor. This parallel configuration
reduces configuration time by using eight data lines to send configuration
data versus one data line in serial configuration.
APEX II devices support multi-voltage configuration; device
configuration can be performed at 3.3 V and 2.5 V or 1.8 V.
Altera Corporation
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