EP2A15 Datasheet, PDF (60/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
General-
Purpose PLLs
Signals can be driven into APEX II devices before and during power-up
without damaging the device. In addition, APEX II devices do not drive
out during power-up. Once operating conditions are reached and the
device is configured, APEX II devices operate as specified by the user.
APEX II devices have ClockLock, ClockBoost, and ClockShift features,
which use four general-purpose PLLs (separate from the four dedicated
True-LVDS PLLs) to provide clock management and clock-frequency
synthesis. These PLLs allow designers to increase performance and
provide clock-frequency synthesis. The PLL reduces the clock delay
within a device. This reduction minimizes clock-to-output and setup
times while maintaining zero hold times. The PLLs, which provide
programmable multiplication, allow the designer to distribute a low-
speed clock and multiply that clock on-device. APEX II devices include a
high-speed clock tree: unlike ASICs, the user does not have to design and
optimize the clock tree. The PLLs work in conjunction with the APEX II
device’s high-speed clock to provide significant improvements in system
performance and bandwidth.
The PLLs in APEX II devices are enabled through the Quartus II software.
External devices are not required to use these features. Table 15 shows the
general-purpose PLL features for APEX II devices. Figure 35 shows an
APEX II general-purpose PLL.
Table 15. APEX II General-Purpose PLL Features
Number of PLLs
4
ClockBoost
Feature
m/(n × k, v)
Number of External
Clock Outputs
8
Number of
Feedback Inputs
2
Figure 35. APEX II General-Purpose PLL Note (1)
inclock
n
Phase
Comparator
Voltage-Controlled
Oscillator
Phase Shift
Circuitry
k
m
v
clock0
clock1
fbin
60
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