EP2A15 Datasheet, PDF (29/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Figure 17. Bidirectional Dual-Port Memory Configuration
A
data_A[ ]
addressA[ ]
wrenA
clockA
clocken_A
q_A[ ]
aclrA
B
data_B[ ]
addressB[ ]
wrenB
clockB
clockenB
q_B[ ]
aclrB
In addition to bidirectional dual-port memory, the ESB also supports
dual-port, and single-port RAM. Dual-port memory supports a
simultaneous read and write. Single-port memory supports independent
read and write. Figure 18 shows these different RAM memory port
configurations for an ESB.
Figure 18. Dual- & Single-Port Memory Configurations
Dual-Port Memory
data[ ]
wraddress[ ]
wren
inclock
inclocken
inaclr
rdaddress[ ]
rden
q[ ]
outclock
outclocken
outaclr
Single-Port Memory (1)
data[ ]
address[ ]
wren
inclock
inclocken
inaclr
q[ ]
outclock
outclocken
outaclr
Note to Figure 18:
(1) Two single-port memory blocks can be implemented in a single ESB.
Altera Corporation
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