EP2A15 Datasheet, PDF (35/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
CAM can generate outputs in three different modes: single-match mode,
multiple-match mode, and fast multiple-match mode. In each mode, the
ESB outputs the matched data’s location as an encoded or unencoded
address. When encoded, the ESB outputs an encoded address of the data’s
location. For instance, if the data is located in address 12, the ESB output
is 12. When unencoded, each ESB port uses its 16 outputs to show the
location of the data over two clock cycles. In this case, if the data is located
in address 12, the 12th output line goes high. Figures 21 and 22 show the
encoded CAM outputs and unencoded CAM outputs, respectively.
Figure 22. Encoded CAM Address Outputs
data[31..0] = 45
CAM
Data Address
15
10
27
11
45
12
85
13
addr[15..0] = 12
match = 1
Encoded Output
Figure 23. Unencoded CAM Address Outputs
CAM
q0
data[30..0] =45 (1)
Data Address
select (2)
15
10
q12
27
11
45
12
q13
85
13
q14
q15
Unencoded outputs.
q12 goes high to
signify a match.
Notes to Figures 22 and 23:
(1) For an unencoded output, the ESB only supports 31 input data bits. One input bit
is used by the select line to choose one of the two banks of 16 outputs.
(2) If the select input is a 1, then CAM outputs odd words between 1 through 15. If
the select input is a 0, CAM outputs even words between 0 through 14.
In single-match mode, it takes two clock cycles to write into CAM, but
only one clock cycle to read from CAM. In this mode, both encoded and
unencoded outputs are available without external logic. Single-match
mode is better suited for designs without duplicate data in the memory.
Altera Corporation
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