EP2A15 Datasheet, PDF (55/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Figure 33. True-LVDS Transmitter Diagram Notes (1), (2)
J Bits Wide
Transmitter
Channel
Serializer
Data from
LEs
Global Clock
from Receiver
or System Clock
TXOUTCLOCK1
×W
Transmitter
PLL1 _× W
J
Transmitter Channel 1
Transmitter
Channel
Transmitter Channel 2
Transmitter
Channel
Transmitter Channel 18
Notes to Figure 33:
(1) Two sets of 18 transmitter channels are located in each APEX II device. Each set of 18 channels has one transmitter
PLL.
(2) W = 1, 2, 4 to 10
J = 1, 2, 4 to 10
W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, DDR I/O registers are used.
Clock-Data Synchronization
In addition to dedicated serial-to-parallel converters, APEX II True-LVDS
circuitry contains CDS circuitry in every receiver channel. The CDS
feature can be turned on or off independently for each receiver channel.
There are two modes for the CDS circuitry: single-bit mode, which
corrects a fixed clock-to-data skew of up to ±50% of the data bit period,
and multi-bit mode, which corrects any fixed clock-to-data skew.
Altera Corporation
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