EP2A15 Datasheet, PDF (41/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Figure 27. Column IOE Connection to the Interconnect
Each IOE can drive column and FastRow
interconnects. Each IOE data and
OE signal is driven by local interconnect.
IOE
IOE
An LE or ESB can drive a
pin through a local
interconnect for faster
clock-to-output times.
LAB
Any LE or ESB can drive
a column pin through a
row, column, and MegaLAB
interconnect.
Column Interconnect
Row Interconnect
MegaLAB Interconnect
FastRow interconnects connect a column I/O pin directly to the LAB local
interconnect within two MegaLAB structures. This feature provides fast
setup times for pins that drive high fan-outs with complex logic, such as
PCI designs. For fast bidirectional I/O timing, LE registers using local
routing can improve setup times and OE timing.
APEX II devices have a peripheral control bus made up of 12 signals that
drive the IOE control signals. The peripheral bus is composed of six
output enables, OE[5:0] and six clock enables, CE[5:0]. These twelve
signals can be driven from internal logic or from the Fast I/O signals.
Table 7 lists the peripheral control signal destinations.
Altera Corporation
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