EP2A15 Datasheet, PDF (75/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Figures 38 and 39 show receiver input and transmitter output waveforms,
respectively, for all differential I/O standards (LVDS, 3.3-V PCML,
LVPECL, and HyperTransport technology).
Figure 38. Receiver Input Waveforms for Differential I/O Standards
Single-Ended Waveform
V_CM
±V_ID
Positive Channel (p) = V_IH
Negative Channel (n) = V_IL
Ground
Differential Waveform
+V_ID
V_{ID (Peak-to-Peak)}
p−n=0V
− V_ID
Figure 39. Transmitter Output Waveforms for Differential I/O Standards
Single-Ended Waveform
V_CM
±V_OD
Positive Channel (p) = V_OH
Negative Channel (n) = V_OL
Ground
Differential Waveform
+V_OD
V_SS (1)
Note to Figure 39:
(1) V_SS: steady-state differential output voltage.
p−n=0V
− V_OD
Tables 42 through 45 provide information on absolute maximum ratings,
recommended operating conditions, and DC operating conditions for
1.5-V APEX II devices.
Altera Corporation
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