EP2A15 Datasheet, PDF (79/99 Pages) Altera Corporation – Programmable Logic Device Family

Timing Model
APEX II Programmable Logic Device Family Data Sheet
The high-performance FastTrack and MegaLAB interconnect routing
structures ensure predictable performance, and accurate simulation and
timing analysis. In contrast, the unpredictable performance of FPGAs is
caused by their segmented connection scheme.
All specifications are always representative of worst-case supply voltage
and junction temperature conditions. All output-pin-timing specifications
are reported for maximum drive strength.
Figure 41 shows the f_MAX timing model for APEX II devices. These
parameters can be used to estimate f_MAX for multiple levels of logic.
However, the Quartus II software timing analysis provides more accurate
timing information because the Quartus II software usually has more up-
to-date timing information than the data sheet until the timing model is
final. Also, the Quartus II software can model delays caused by loading
and distance effects more accurately than by using the numbers in this
data sheet.
Altera Corporation
79