EP2A15 Datasheet, PDF (6/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
After an APEX II device has been configured, it can be reconfigured in-
circuit by resetting the device and loading new data. Real-time changes
can be made during system operation, enabling innovative reconfigurable
computing applications.
Functional
Description
Software
APEX II devices are supported by the Altera Quartus II development
system: a single, integrated package that offers hardware description
language (HDL) and schematic design entry, compilation and logic
synthesis, full simulation and worst-case timing analysis, SignalTap logic
analysis, and device configuration. The Quartus II software runs on
Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800
workstations.
The Quartus II software includes the LogicLock incremental design
feature. The LogicLock feature allows the designer to make pin and
timing assignments, verify functionality and performance, and then set
constraints to lock down the placement and performance of a specific
block of logic using LogicLock constraints. Constraints set by the
LogicLock function guarantee repeatable placement when implementing
a block of logic in a current project or exporting the block to another
project. The constraints set by the LogicLock feature can lock down logic
to a fixed location in the device. The LogicLock feature can also lock the
logic down to a floating location, and the Quartus II software determines
the best relative placement of the block to meet design requirements.
Adding additional logic to a project will not affect the performance of
blocks locked down with LogicLock constraints.
The Quartus II software provides NativeLink interfaces to other industry-
standard PC- and UNIX workstation-based EDA tools. For example,
designers can open the Quartus II software from within third-party
design tools. The Quartus II software also contains built-in optimized
synthesis libraries; synthesis tools can use these libraries to optimize
designs for APEX II devices. For example, the Synopsys Design Compiler
library, supplied with the Quartus II development system, includes
DesignWare functions optimized for the APEX II architecture.
APEX II devices incorporate LUT-based logic, product-term-based logic,
memory, and high-speed I/O standards into one device. Signal
interconnections within APEX II devices (as well as to and from device
pins) are provided by the FastTrack interconnect—a series of fast,
continuous row and column channels that run the entire length and width
of the device.
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Altera Corporation