EP2A15 Datasheet, PDF (12/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Figure 5. APEX II Logic Element
Carry-In
LAB-wide LAB-wide
Synchronous Synchronous
Load
Clear
Cascade-In
data1
data2
data3
data4
Look-Up
Table
(LUT)
Carry
Chain
Cascade
Chain
Synchronous
Load & Clear
Logic
labclr1
labclr2
Chip-Wide
Reset
labclk1
labclk2
labclkena1
labclkena2
Asynchronous
Clear/Preset/
Load Logic
Clock &
Clock Enable
Select
Carry-Out
Cascade-Out
Register Bypass
Packed
Register Select
Programmable
Register
PRN
DQ
ENA
CLRN
To FastTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
To FastTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. The register’s clock and clear control signals can be driven by
global signals, general-purpose I/O pins, or any internal logic. For
combinatorial functions, the register is bypassed and the output of the
LUT drives the outputs of the LE.
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Altera Corporation