EP2A15 Datasheet, PDF (72/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Table 34. SSTL-3 Class II Specifications
Symbol
V_CCIO
V_TT
V_REF
V_IH
V_IL
V_OH
V_OL
Parameter
Output supply voltage
Termination voltage
Reference voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Conditions Minimum
3.0
V_REF – 0.05
1.3
V_REF + 0.2
–0.3
I_OH = –16 mA
(10)
V_{T T} + 0.8
I_OL = 16 mA (10)
Typical
3.3
V_REF
1.5
Maximum
3.6
V_REF + 0.05
1.7
V_CCIO + 0.3
V_REF – 0.2
V_TT – 0.8
Units
V
V
V
V
V
V
V
Table 35. 3.3-V AGP 2× Specifications
Symbol
V_CCIO
V_REF
V_IH
V_IL
V_OH
V_OL
I_I
Parameter
Conditions Minimum
Output supply voltage
3.15
Reference voltage
High-level input voltage
(11)
0.39 × V_CCIO
0.5 × V_CCIO
Low-level input voltage (11)
High-level output voltage
Low-level output voltage
Input pin leakage current
I_OUT = –20 µA
I_OUT = 20 µA
0 < V_{I N} < V_CCIO
0.9 × V_CCIO
–10
Typical
3.3
Maximum
3.45
0.41 × V_CCIO
V_CCIO + 0.5
0.3 × V_CCIO
3.6
0.1 × V_CCIO
10
Units
V
V
V
V
V
V
µA
Table 36. 3.3-V AGP 1× Specifications
Symbol
V_CCIO
V_IH
V_IL
V_OH
V_OL
I_I
Parameter
Conditions Minimum
Output supply voltage
High-level input voltage
(11)
Low-level input voltage (11)
High-level output voltage
Low-level output voltage
Input pin leakage current
I_OUT = –20 µA
I_OUT = 20 µA
0 < V_{I N} < V_CCIO
3.15
0.5 × V_CCIO
0.9 × V_CCIO
–10
Typical
3.3
Maximum
3.45
V_CCIO + 0.5
0.3 × V_CCIO
3.6
0.1 × V_CCIO
10
Units
V
V
V
V
V
µA
72
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