EP2A15 Datasheet, PDF (80/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Figure 41. f_MAX Timing Model
LE
t _SU
t_H
t _CO
t _LUT
ESB
t _ESBARC
t _ESBSRC
t _ESBAWC
t _ESBSWC
t _ESBWASU
t _ESBWDSU
t _ESBSRASU
t _ESBWESU
t _ESBDATASU
t _ESBWADDRSU
t _ESBRADDRSU
t _ESBDATACO1
t _ESBDATACO2
t _ESBDD
t _PD
t _PTERMSU
t _PTERMCO
Routing Delay
t _F1—4
t _F5—20
t _F20+
80
Altera Corporation