EP2A15 Datasheet, PDF (76/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Table 42. 3.3-V LVDS I/O Specifications
Symbol
V_CCIO
V_OD
∆ V_OD
V_OS
∆ V_OS
V_TH
V_IN
R_L
Parameter
Conditions
I/O supply voltage
Differential output voltage
Change in V_OD between
high and low
R_L = 100 Ω
R_L = 100 Ω
Output Offset voltage
Change in V_OS between
high and low
R_L = 100 Ω
R_L = 100 Ω
Differential input threshold V_CM = 1.2 V
Receiver input voltage
range
Receiver differential input
resistor (external to
APEX II devices)
Minimum
3.135
250
Typical
3.3
Maximum
3.465
850 (1)
50
Units
V
mV
mV
1.125
1.25
1.375
V
50
mV
–100
0.0
100
mV
2.4
V
90
100
110
Ω
Table 43. 3.3-V PCML Specifications
Symbol
V_CCIO
V_IL
Parameter
I/O supply voltage
Low-level input voltage
V_IH
High-level input voltage
V_OL
Low-level output voltage
V_OH
High-level output voltage
V_T
Output termination voltage
V_OD
Differential output voltage
t_R
Rise time (20 to 80%)
t_F
Fall time (20 to 80%)
R_O
Output load
R_L
Receiver differential input
resistor
Conditions
Minimum
3.135
V_CCIO
V_CCIO –
0.6
V_CCIO
300
85
85
45
Typical
3.3
V_CCIO
450
100
50
Maximum
3.465
V_CCIO –
0.3
V_CCIO –
0.3
V_CCIO –
0.3
600
325
325
55
Units
V
V
V
V
V
V
mV
ps
ps
Ω
Ω
76
Altera Corporation