EP2A15 Datasheet, PDF (92/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Table 67. EP2A70 Minimum Pulse Width Timing Parameters
Symbol
-7 Speed Grade
-8 Speed Grade
-9 Speed Grade
Unit
t_CH
t_CL
t_CLRP
t_PREP
t_ESBCH
t_ESBCL
t_ESBWP
t_ESBRP
Min
Max
Min
Max
Min
Max
1.19
1.19
0.16
0.16
1.19
1.19
1.35
1.13
1.78
1.78
0.19
0.19
1.78
1.78
1.56
1.30
2.53
ns
2.53
ns
0.21
ns
0.21
ns
2.53
ns
2.53
ns
1.79
ns
1.50
ns
Tables 68 through 77 show the IOE external timing parameter values for
APEX II devices.
Table 68. EP2A15 External Timing Parameters for Row I/O Pins
Symbol
-7 Speed Grade
-8 Speed Grade
t_INSU
t_INH
t_OUTCO
t_XZ
t_ZX
t_INSUPLL
t_INHPLL
t_OUTCOPLL
t_XZPLL
t_ZXPLL
Min
Max
Min
Max
2.06
2.25
0.00
0.00
2.00
4.05
2.00
4.45
4.98
5.59
4.98
5.59
1.15
1.28
0.00
0.00
0.50
2.60
0.50
2.87
3.53
4.00
3.53
4.00
-9 Speed Grade
Unit
Min
Max
2.46
ns
0.00
ns
2.00
4.90
ns
6.26
ns
6.26
ns
1.42
ns
0.00
ns
0.50
3.16
ns
4.52
ns
4.52
ns
92
Altera Corporation