EP2A15 Datasheet, PDF (49/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Bus Hold
Each APEX II device I/O pin provides an optional bus-hold feature. When
this feature is enabled for an I/O pin, the bus-hold circuitry weakly holds
the signal at its last driven state. By holding the last driven state of the pin
until the next input signal is present, the bus-hold feature eliminates the
need to add external pull-up or pull-down resistors to hold a signal level
when the bus is tri-stated. The bus-hold circuitry also pulls undriven pins
away from the input threshold voltage where noise can cause unintended
high-frequency switching. This feature can be selected individually for
each I/O pin. The bus-hold output will drive no higher than V_CCIO to
prevent overdriving signals. If the bus-hold feature is enabled, the
programmable pull-up option cannot be used. The bus-hold feature
should also be disabled if open-drain outputs are used with the GTL+ I/O
standard.
The bus-hold circuitry weakly pulls the signal level to the last driven state
through a resistor with a nominal resistance (R_BH) of approximately 7 kΩ.
Table 41 on page 74 gives specific sustaining current that will be driven
through this resistor and overdrive current that will identify the next
driven input level. This information is provided for each V_CCIO voltage
level.
The bus-hold circuitry is active only after configuration. When going into
user mode, the bus-hold circuit captures the value on the pin present at
the end of configuration.
Programmable Pull-Up Resistor
Each APEX II device I/O pin provides an optional programmable pull-up
resistor during user mode. When this feature is enabled for an I/O pin, the
pull-up resistor (typically 25 kΩ) weakly holds the output to the V_CCIO
level of the bank that the output pin resides in.
Dedicated Fast I/O Pins
APEX II devices incorporate dedicated bidirectional pins for signals with
high internal fanout, such as PCI control signals. These pins are called
dedicated fast I/O pins (FAST1, FAST2, FAST3, and FAST4) and can
drive the four global fast lines throughout the device, ideal for fast clock,
clock enable, preset, clear, or high fanout logic signal distribution. The
dedicated fast I/O pins have one output register and one OE register, but
they do not have input registers. The dedicated fast lines can also be
driven by a LE local interconnect to generate internal global signals.
Altera Corporation
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