EP2A15 Datasheet, PDF (95/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Table 73. EP2A40 External Timing Parameters for Column I/O Pins
Symbol
-7 Speed Grade
-8 Speed Grade
t_INSU
t_INH
t_OUTCO
t_XZ
t_ZX
t_INSUPLL
t_INHPLL
t_OUTCOPLL
t_XZPLL
t_ZXPLL
Min
Max
Min
Max
2.00
2.16
0.00
0.00
2.00
4.96
2.00
5.29
7.04
7.59
7.04
7.59
1.20
1.31
0.00
0.00
0.50
2.66
0.50
2.87
4.74
5.17
4.74
5.17
Table 74. EP2A70 External Timing Parameters for Row I/O Pins
Symbol
-7 Speed Grade
-8 Speed Grade
t_INSU
t_INH
t_OUTCO
t_XZ
t_ZX
t_INSUPLL
t_INHPLL
t_OUTCOPLL
t_XZPLL
t_ZXPLL
Min
Max
Min
Max
2.48
2.68
0.00
0.00
2.00
4.76
2.00
5.12
5.68
6.19
5.68
6.19
1.19
1.30
0.00
0.00
0.50
2.52
0.50
2.74
3.44
3.82
3.44
3.82
-9 Speed Grade
Unit
Min
Max
2.33
ns
0.00
ns
2.00
5.64
ns
8.19
ns
8.19
ns
1.43
ns
0.00
ns
0.50
3.09
ns
5.64
ns
5.64
ns
-9 Speed Grade
Unit
Min
2.90
0.00
2.00
1.43
0.00
0.50
Max
ns
ns
5.51
ns
6.76
ns
6.76
ns
ns
ns
2.98
ns
4.23
ns
4.23
ns
Altera Corporation
95