EP2A15 Datasheet, PDF (24/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Table 5 summarizes how elements of the APEX II architecture drive each
other.
Table 5. APEX II Routing Scheme
Source
Row Column LE
I/O Pin I/O Pin
Row I/O pin
Column I/O
pin
LE
ESB
Local
vv v
interconnect
MegaLAB
interconnect
Row
FastTrack
interconnect
Column
FastTrack
interconnect
FastRow
interconnect
Destination
ESB
Local
MegaLAB
Row
Column FastRow
Interconnect Interconnect FastTrack FastTrack Interconnect
Interconnect Interconnect
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Product-Term Logic
The product-term portion of the MultiCore architecture is implemented
with the ESB. The ESB can be configured to act as a block of macrocells on
an ESB-by-ESB basis. 32 inputs from the adjacent local interconnect feed
each ESB; therefore, the either MegaLAB or the adjacent LAB can drive the
ESB. Also, nine ESB macrocells feed back into the ESB through the local
interconnect for higher performance. Dedicated clock pins, global signals,
and additional inputs from the local interconnect drive the ESB control
signals.
In product-term mode, each ESB contains 16 macrocells. Each macrocell
consists of two product terms and a programmable register. Figure 13
shows the ESB in product-term mode.
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Altera Corporation