TLK10031 Datasheet, PDF (88/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
www.ti.com
7.5.2.43 LATENCY_MEASURE_CONTROL (register = 0x8040) (default = 0x0000)
(device address: 0x1E)
Figure 7-83. LATENCY_MEASURE_CONTROL Register
15
14
13
12
11
10
9
8
RESERVED
RW
7
6
5
4
3
2
LATENCY_MEAS_STOP_SEL[1: LATENCY_MEAS_CLK_DIV[1:0 ] LATENCY_MEAS_START_SEL[
0]
(RXG)
1:0]
(RXG)
(RXG)
RW
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
1
0
LATENCY_ME LATENCY_ME
AS_EN
AS_CLK_SEL
(RXG)
(RXG)
RW
Table 7-64. LATENCY_MEASURE_CONTROL Field Descriptions
Bit Field
15:8 RESERVED
7:6 LATENCY_MEAS_STOP_SEL[1: 0]
(RXG)
5:4 LATENCY_MEAS_CLK_DIV[1:0 ]
(RXG)
3:2 LATENCY_MEAS_START_SEL[ 1:0]
(RXG)
1 LATENCY_MEAS_EN
(RXG)
0 LATENCY_MEAS_CLK_SEL
(RXG)
Type
RW
RW
RW
RW
RW
RW
Reset
Description
For TI use only. Always reads 0.
Latency measurement stop point selection
00 = Selects LS RX as stop point (Default 2 ’b00)
01 = Selects HS TX as stop point
1x = Selects external pin (PRTAD0) as stop point
Latency measurement clock divide control. Valid only when bit 1E.8040 bit 2 is 0.
Divides clock to needed resolution. Higher the divide value, lesser the latency
measurement resolution. Divider value should be chosen such that the divided clock
doesn’t result in clock slower than the high speed byte clock.
00 = Divide by 1 (Default 2’b00) (Most Accurate Measurement)
01 = Divide by 2
10 = Divide by 4
11 = Divide by 8 (Longest Measurement Capability)
Latency measurement start point selection
00 = Selects LS TX as start point (Default 2’b00)
01 = Selects HS RX as start point
1x = Selects external pin (PRTAD0) as start point
Latency measurement enable
0 = Disable Latency measurement (Default ’b0)
1 = Enable Latency measurement
Latency measurement clock selection.
0 = Selects VCO clock as per Latency measurement table. Bits 1E.8040 bits 5:4 can
be used to divide this clock to achieve needed resolution. (Default 1’b0)
1 = Selects recovered byte clock
7.5.2.44 LATENCY_COUNTER_2 (register = 0x8041) (default =0x0000)
(device address: 0x1E)
Figure 7-84. LATENCY_COUNTER_2 Register
15
14
13
12
LATENCY_MEAS_START_COMMA[3:0]
(RXG)
RO/LH
11
10
9
8
LATENCY_MEAS_STOP_COMMA[3:0]
(RXG)
RO/LH
7
6
5
4
RESERVED
LATENCY_
MEAS_READY
(RXG)
RO/LH
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
2
1
0
LATENCY_MEAS_COUNT[19:16]
(RXG)
RO
88
Detailed Description
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