TLK10031 Datasheet, PDF (67/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
7.5.2.10 HS_OVERLAY_CONTROL (register: 0x0009) (default: 0x0380) (device address: 0x1E)
Figure 7-50. HS_OVERLAY_CONTROL Register
15
14
13
12
11
LS_OK_OUT_GATE[1:0]
(G)
LS_OK_IN_GATE[1:0]
(G)
R/W
R/W
10
9
RESERVED
R/W
7
6
5
4
HS_LOS_
MASK
(G)
RESERVED
HS_CH_SYNC
_OVERLAY
(RXG)
HS_INVALID_
CODE_
OVERLAY
(RXG)
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
HS_AGCLOCK
_
OVERLAY
(RXG)
R/W
2
1
HS_AZDONE_ HS_PLL_LOCK
OVERLAY
_OVERLAY
(RXG)
(RXG)
R/W
R/W
8
0
HS_LOS_
OVERLAY
(RXG)
R/W
Table 7-31. HS_OVERLAY_CONTROL Field Description
Bit
15:14
Field
LS_OK_OUT_GATE[1:0]
(G)
13:12 LS_OK_IN_GATE[1:0]
(G)
11:8 RESERVED
7 HS_LOS_MASK
(G)
6 RESERVED
5 HS_CH_SYNC_OVERLAY
(RXG)
4 HS_INVALID_CODE_OVERLAY
(RXG)
3 HS_AGCLOCK_OVERLAY
(RXG)
2 HS_AZDONE_OVERLAY
(RXG)
1 HS_PLL_LOCK_OVERLAY
(RXG)
0 HS_LOS_OVERLAY
(RXG)
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
X0
01
11
X0
01
11
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
LS_OK_OUT_A gating control
Gating disabled (Default 2’b00)
Gating enabled. LS_OK_OUT_A gated to LOW
Gating enabled. LS_OK_OUT_A gated to HIGH
LS_OK_IN_A gating control
Gating disabled (Default 2’b00)
Gating enabled.LS_OK_IN_A gated to LOW
Gating enabled.LS_OK_IN_A gated to HIGH
For TI use only. (Default 4’b0011)
HS Serdes LOS status is used to generate HS channel synchronization status. If HS
Serdes indicates LOS, channel synchronization indicates synchronization is not
achieved
HS Serdes LOS status is not used to generate HS channel synchronization status
(Default 1’b1)
For TI use only. Always reads 0.
LOSA pin does not reflect receive channel loss of block lock (Default 1’b0)
Allows channel loss of block lock to be reflected on LOSA pin
LOSA pin does not reflect receive channel invalid code word error (Default 1’b0)
Allows invalid code word error to be reflected on LOSA pin
0 = LOSA pin does not reflect HS Serdes AGC unlock status (Default 1’b0)
Allows HS Serdes AGC unlock status to be reflected on LOSApin
LOSA pin does not reflect HS Serdes auto zero calibration not done status (Default
1’b0)
Allows auto zero calibration not done status to be reflected on LOSA pin
LOSA pin does not reflect loss of HS Serdes PLL lock status (Default 1’b0)
Allows HS Serdes loss of PLL lock status to be reflected onLOSApin
LOSA pin does not reflect HS Serdes Loss of signal condition (Default 1’b0)
Allows HS Serdes Loss of signal condition to be reflected on LOSA pin
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