TLK10031 Datasheet, PDF (111/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
7.5.3.38 KR_VS_RX_CTC_INSERT_COUNT (register = 0x8017) (default = 0xFFFD)
(device address: 0x01)
Figure 7-125. KR_VS_RX_CTC_INSERT_COUNT Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RX_CTC_INS_COUNT
(R)
COR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-107. KR_VS_RX_CTC_INSERT_COUNT Field Descriptions
Bit Field
15:0 RX_CTC_INS_COUNT
(R)
Type
COR
Reset
Description
Counter for number of idle inserts in the receive CTC.
7.5.3.39 KR_VS_STATUS_1 (register = 0x8018) (default = 0x0000) (device address: 0x01)
Figure 7-126. KR_VS_STATUS_1 Register
15
14
13
12
11
10
9
8
TX_TPV_TP_
SYNC
(R)
RESERVED
RO
RO
7
6
5
4
RESERVED
INVALID_S_
COL_ERR
(R)
INVALID_T_
COL_ERR
(R)
RO
RO/LH
RO/LH
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
2
1
0
INVALID_XGMI INVALID_XGMI INVALID_XGMI INVALID_XGMI
I_LN3
I_LN2
I_LN1
I_LN0
(R)
(R)
(R)
(R)
RO/LH
RO/LH
RO/LH
RO/LH
Bit Field
15 TX_TPV_TP_SYNC
(R)
14:6 RESERVED
5 INVALID_S_COL_ERR
(R)
4 INVALID_T_COL_ERR
(R)
3 INVALID_XGMII_LN3
(R)
2 INVALID_XGMII_LN2
(R)
1 INVALID_XGMII_LN1
(R)
0 INVALID_XGMII_LN0
(R)
Table 7-108. KR_VS_STATUS_1 Field Descriptions
Type
RO
Reset
RO
RO/LH
Description
0 = Test pattern sync is not achieved on on Tx side
1 = Test pattern sync is achieved on on Tx side
For TI use only
1 = Indicates invalid start (S) column error detected
RO/LH
1 = Indicates invalid terminate (T) column error detected
RO/LH
1 = Indicates invalid XGMII character detected in Lane 3
RO/LH
1 = Indicates invalid XGMII character detected in Lane 2
RO/LH
1 = Indicates invalid XGMII character detected in Lane 1
RO/LH
1 = Indicates invalid XGMII character detected in Lane 0
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