TLK10031 Datasheet, PDF (45/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
7.4.17 MDIO Management Interface
The TLK10031 supports the Management Data Input/Output (MDIO) Interface as defined in Clauses 22
and 45 of the IEEE 802.3-2008 Ethernet specification. The MDIO allows register-based management and
control of the serial links.
The MDIO Management Interface consists of a bi-directional data path (MDIO) and a clock reference
(MDC). The device identification and port address are determined by control pins (see Section 4). Also,
whether the device responds as a Clause 22 or Clause 45 device is also determined by control pin ST
(see Section 4).
In Clause 45 (ST = 0) and Clause 22 (ST = 1), the top 4 control pins PRTAD[4:1] determine the device
port address. In this mode, TLK10031 responds if the PHY address field on the MDIO protocol (PA[4:1])
matches PRTAD[4:1] pin value, and the PHY address field PA[0] = 0.
In Clause 22 (ST = 1) mode, only 32 (5’b00000 to 5’b11111) register addresses can be accessed through
standard protocol. Due to this limitation, an indirect addressing method (More description in Clause 22
Indirect Addressing section) is implemented to provide access to all device specific control/status registers
that cannot be accessed through the standard Clause 22 register address space.
Write transactions which address an invalid register or device or a read only register will be ignored. Read
transactions which address an invalid register or device will return a 0.
7.4.18 MDIO Protocol Timing
Timing for a Clause 45 address transaction is shown in Figure 7-19. The Clause 45 timing required to
write to the internal registers is shown in Figure 7-20. The Clause 45 timing required to read from the
internal registers is shown in Figure 7-21. The Clause 45 timing required to read from the internal registers
and then increment the active address for the next transaction is shown in Figure 7-22. The Clause 22
timing required to read from the internal registers is shown in Figure 7-23. The Clause 22 timing required
to write to the internal registers is shown in Figure 7-24.
MDC
MDIO
0000
PA[4:0]
DA[4:0]
1
0 A15 A0
1
> 32 "1's"
Preamble
Start
Addr
Code
PHY
Addr
Dev
Addr
Turn
Around
Reg
Addr
Idle
Figure 7-19. CL45 - Management Interface Extended Space Address Timing
MDC
MDIO
0001
PA[4:0]
DA[4:0]
1
0 D15 D0
1
> 32 "1's"
Preamble
Start
Write
Code
PHY
Addr
Dev
Addr
Turn
Around
Data
Idle
Figure 7-20. CL45 - Management Interface Extended Space Write Timing
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