TLK10031 Datasheet, PDF (120/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
www.ti.com
7.5.4.14 PCS_TP_CONTROL (register = 0x002A) (default = 0x0000) (device address: 0x03)
Figure 7-147. PCS_TP_CONTROL Register
15
14
13
12
11
10
9
RESERVED
RW
7
6
5
4
3
2
RESERVED
PCS_PRBS31_ PCS_PRBS31_ PCS_TX_TP_E PCS_RX_TP_E
RX_TP_EN
TX_TP_EN
N
N
(R)
(R)
(R)
(R)
RW
RW
RW
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
1
PCS_TP_SEL
(R)
RW
8
0
PCS_DP_SEL
(R)
RW
Bit Field
15:6 RESERVED
5 PCS_PRBS31_RX_TP_EN
(R)
4 PCS_PRBS31_TX_TP_EN
(R)
3 PCS_TX_TP_EN
(R)
2 PCS_RX_TP_EN
(R)
1 PCS_TP_SEL
(R)
0 PCS_DP_SEL
(R)
Table 7-129. PCS_TP_CONTROL Field Descriptions
Type
RW
RW
Reset
RW
RW
RW
RW
RW
Description
For TI use only. Always reads 0.
1 = Enable PRBS31 test pattern verification on receive path
0 = Normal operation (Default 1’b0)
1 = Enable PRBS31 test pattern generation on transmit path
0 = Normal operation (Default 1’b0)
1 = Enable transmit test pattern generation
0 = Normal operation (Default 1’b0)
1 = Enable receive test pattern verification
0 = Normal operation (Default 1’b0)
1 = Square wave test pattern
0 = Pseudo random test pattern (Default 1’b0)
1 = 0’S data pattern
0 = LF data pattern (Default 1’b0)
7.5.4.15 PCS_TP_ERR_COUNT (register = 0x002B) (default = 0x0000) (device address: 0x03)
Figure 7-148. PCS_TP_ERR_COUNT Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PCS_TP_ERR_COUNT[15:0]
(R)
COR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-130. PCS_TP_ERR_COUNT Field Descriptions
Bit Field
15:0 PCS_TP_ERR_COUNT[15:0]
(R)
Type
COR
Reset
Description
Test pattern error counter. This counter reflects number of errors occurred during the
test pattern mode selected through PCS_TP_CONTROL. In PRBS31 test pattern
verification mode, counter value indicates the number of received bytes that have 1 or
more bit errors.
120 Detailed Description
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