TLK10031 Datasheet, PDF (37/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

www.ti.com
TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
3. Mark all the common frequencies that appear on both SERDES sides. Note and discard all those that
fall outside the allowed range. In this example, the common frequencies are highlighted in Table 7-9.
The highest and lowest computed reference clock frequencies must be discarded because they
exceed the recommended range.
4. Select any of the remaining marked common reference clock frequencies. Higher reference clock
frequencies are generally preferred. In this example, any of the following reference clock frequencies
can be selected: 397.4MHz, 331.167MHz, 248.375MHz, 198.7MHz, 165.583MHz, 158.96MHz, and
132.467MHz
Table 7-9. Reference Clock Frequency Selection Example
LOW SPEED SIDE SERDES
SERDES PLL ^{REFERENCE CLOCK FREQUENCY (MHz)}
MULTIPLIER _COMPUTED
MIN
MAX
4
496.750
250
425
5
397.400
200
425
6
331.167
166.667
416.667
8
248.375
125
312.5
10
198.700
122.88
250
12
165.583
122.88
208.333
12.5
158.960
122.88
200
15
132.467
122.88
166.667
20
99.350
122.88
125
HIGH SPEED SIDE SERDES
SERDES PLL ^{REFERENCE CLOCK FREQUENCY (MHz)}
MULTIPLIER _COMPUTED
MIN
MAX
4
496.750
375
425
5
397.400
300
425
6
331.167
250
416.667
8
248.375
187.5
312.5
10
198.700
150
250
12
165.583
125
208.333
12.5
158.960
153.6
200
15
132.467
122.88
166.667
20
99.350
122.88
125
7.4.11 General Purpose SERDES Mode Test Pattern Support
The TLK10031 has the capability to generate and verify various test patterns for self-test and system
diagnostic measurements. Most of the same test pattern support is available for 10G General Purpose
Mode as for 10G-KR. (See Register 1E.000B for details).
7.4.12 General Purpose SERDES Mode Latency
The latency through the TLK10031 in General Purpose SERDES mode is as shown in Figure 7-13. Note
that the latency ranges shown indicate static rather than dynamic latency variance, i.e., the range of
possible latencies when the serial link is initially established. During normal operation, the latency through
the device is fixed.
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLK10031
Detailed Description
37