TLK10031 Datasheet, PDF (140/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
www.ti.com
10.1.2.2 External Clock Connections
An external clock jitter cleaner, such as Texas Instruments CDCE72010 or CDCM7005, may be used
when needed to provide a low jitter reference clock. An example external clock jitter cleaner connection for
channel A is shown in Figure 10-5.
HSRXAP/N
OUTA[3:0]
CLKOUTAP/N
REFCLK0P/N
TLK10031
External
Clock Jitter
Cleaner
VCXO
FPGA
HSTXAP/N ^INA[3:0]
Figure 10-5. An External Clock Jitter Cleaner Connection Example for Channel A
10.1.2.3 TLK10031 Control Pins and Interfaces
The TLK10031 device features a number of control pins and interfaces, some of which are described as
follows.
10.1.2.3.1 MDIO Interface
The TLK10031 supports the Management Data Input/Output (MDIO) Interface as defined in Clause 22 of
the IEEE 802.3 Ethernet specification. The MDIO allows register-based management and control of the
serial links.
The MDIO Management Interface consists of a bi-directional data path (MDIO) and a clock reference
(MDC). The port address is determined by the PRTAD[4:0] control pins.
The MDIO pin requires a pullup to VDDO[1:0]. No pullup is needed on the MDC pin if driven with a push-
pull MDIO master, but a pullup to VDDO[1:0] is needed if driven with an open-drain MDIO master.
10.1.2.3.2 JTAG Interface
The JTAG interface is mostly used for device test. The JTAG interface operates through the TDI, TDO,
TMS, TCK, and TRST_N pins. If not used, all the pins can be left unconnected except TDI and TCK which
must be grounded.
10.1.2.3.3 Unused Pins
As a general guideline, any unused LVCMOS input pin needs to be grounded and any unused LVCMOS
output pin can be left unconnected. Unused CML differential output pins can be left unconnected. Unused
CML differential input pins should be tied to ground through a shared 100-Ω resistor.
140 Layout
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