TLK10031 Datasheet, PDF (25/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
7.3.14 10GBASE-KR Auto-Negotiation
When TLK10031 is selected to operate in 10GKR/1G-KX mode (MODE_SEL pin held low), Clause 73
Auto-Negotiation will commence after power up or hardware or software reset. The data path chosen from
the result of Auto-Negotiation will be the highest speed of 10G-KR or 1G-KX as advertised in the MDIO
ability fields (set to 10G-KR by default). If 10G-KR is chosen, link training will commence immediately
following the completion of Auto-Negotiation. Legacy devices that operate in 1G-KX mode and do not
support Clause 73 Auto Negotiation will be recognized through the Clause 73 parallel detection
mechanism.
7.3.15 10GBASE-KR Link Training
Link training for 10G-KR mode is performed after auto-negotiation, and follows the procedure described in
IEEE 802.3-2008. The high speed TX SERDES side will update pre-emphasis tap coefficients as
requested through the Coefficient update field. Received training patterns are monitored for bit errors
(MDIO configurable), and requests are made to update partner channel TX coefficients until optimal
settings are achieved.
The RX link training algorithm consists of sending a series of requests to move the link partner’s
transmitter tap coefficients to the center point of an error free region. Once link training has completed, the
10G-KR data path is enabled. If link is lost, the entire process repeats with auto-negotiation, link training,
and 10G-KR mode.
TLK10031 also offers a manual mode whereby coefficient update requests are handled through external
software management.
7.3.16 10GBASE-KR Line Rate, PLL Settings, and Reference Clock Selection
The TLK10031 includes internal low-jitter high quality oscillators that are used as frequency multipliers for
the low speed and high speed SERDES and other internal circuits of the device. Specific MDIO registers
are available for SERDES rate and PLL multiplier selection to match line rates and reference clock
(REFCLK0/1) frequencies for various applications.
The external differential reference clock has a large operating frequency range allowing support for many
different applications. A low-jitter reference clock should be used, and its frequency accuracy should be
within ±200 PPM of the incoming serial data rate (±100 PPM of nominal data rate).
When the TLK10031 device is set to operate in the 10GBASE-KR mode with a low speed side line rate of
3.125 Gbps and a high speed side line rate of 10.3125 Gbps, the reference clock choices are as shown in
Table 7-1. In general, using a higher reference clock frequency results in improved jitter performance.
Table 7-1. Specific Line Rate and Reference Clock Selection for the 10GBASE-KR Mode:
Line Rate
(Mbps)
3125
3125
LOW SPEED SIDE
SERDES PLL
Multiplier
Rate
10
Full
5
Full
REFCLKP/N
(MHz)
156.25
312.5
Line Rate
(Mbps)
10312.5
10312.5
HIGH SPEED SIDE
SERDES PLL
Multiplier
Rate
16.5
Full
8.25
Full
REFCLKP/N
(MHz)
156.25
312.5
7.3.17 10GBASE-KR Test Pattern Support
The TLK10031 has the capability to generate and verify various test patterns for self-test and system
diagnostic measurements. The following test patterns are supported:
• High Speed (HS) Side: PRBS 2⁷ – 1, PRBS 2²³ – 1, PRBS 2³¹ – 1, Square Wave with Provisionable
Length, and KR Pseudo-Random Pattern
• Low Speed (LS) Side: PRBS 2⁷ – 1, PRBS 2²³ – 1, PRBS 2³¹ – 1, High Frequency, Low Frequency,
Mixed Frequency, CRPAT, CJPAT.
Copyright © 2015, Texas Instruments Incorporated
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