TLK10031 Datasheet, PDF (18/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
www.ti.com
7 Detailed Description
7.1 Overview
Various interfaces of the TLK10031 device are shown in Figure 7-1. A simplified block diagram of both the
transmit and receive data path is shown in Figure 7-2. This low-power transceiver consists of two
serializer/deserializer (SERDES) blocks, one on the low speed side and the other on the high speed side.
The core logic block that lies between the two SERDES blocks carries out all the logic functions including
channel synchronization, lane alignment, 8B/10B and 64B/66B encoding/decoding, as well as test pattern
generation and verification.
The TLK10031 provides a management data input/output (MDIO Clause 22/45) interface as well as a
JTAG interface for device configuration, control, and monitoring. Detailed description of the TLK10031 pin
functions is provided in Section 4.
7.2 Functional Block Diagrams
INA0P/N
INA1P/N
INA2P/N
INA3P/N
OUTA0P/N
OUTA1P/N
OUTA2P/N
OUTA3P/N
Low
Speed
Inputs
Low
Speed
Outputs
DATA PATH
High
Speed
Outputs
HSTXAP/N
High
Speed
Inputs
HSRXAP/N
REFCLK0P/N
REFCLK1P/N
REFCLK_SEL
LOSA
LS_OK_IN_A
LS_OK_OUT_A
PDTRXA_N
RESET_N
TESTEN
PRBSEN
PRBS_PASS
GPI0
18
Detailed Description
CLOCKS
CLKOUTAP/N
MDIO
CONTROL,
STATUS, TEST
JTAG
Figure 7-1. TLK10031 Interfaces
PRTAD[4:0]
MDC
MDIO
ST
MODE_SEL
TDO
TMS
TRST_N
TCK
TDI
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