TLK10031 Datasheet, PDF (71/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
7.5.2.14 LS_CONFIG_CONTROL (register: 0x000C) (default: 0x0330) (device address: 0x1E)
Figure 7-54. LS_CONFIG_CONTROL Register
15
14
RESERVED
R/W
13
12
LS_STATUS_CFG[1:0]
(RG)
R/W
11
10
RESERVED
R/W
7
6
5
4
RESERVED
LS_LOS_MAS LS_PLL_LOCK
K
_MASK
(G)
(G)
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
RESERVED
R/W
2
FORCE_LM_R
EALIGN
(G)
R/W
9
8
RESERVED
R/W
1
0
RESERVED
R/W
Bit
15:14
13:12
Field
RESERVED
LS_STATUS_CFG[1:0]
(RG)
11:10
9:8
7:6
5
RESERVED
RESERVED
RESERVED
LS_LOS_MASK
(G)
4
LS_PLL_LOCK_MASK
(G)
3
RESERVED
2
FORCE_LM_REALIGN
(G)
1:0 RESERVED
Table 7-35. LS_CONFIG_CONTROL Field Description
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
00
01
10
11
0
1
0
1
0
1
Description
For TI use only. (Default 2'b00)
Selects selected lane status to be reflected in LS_STATUS_1 register 1E.0015 bit 14
Lane 0 (Default 2’b00)
Lane 1
Lane 2
Lane 3
For TI use only. Always reads 0.
For TI use only. (Default 2’b11)
For TI use only.
LS Serdes LOS status of enabled lanes is used to generate link status
LS Serdes LOS status of enabled lanes is not used to generate link status (Default 1’b1)
LS Serdes PLL Lock status is used to generate link status
LS Serdes PLL Lock status is not used to generate link status (Default 1’b1)
For TI use only. Always reads 0.
Normal operation (Default 1’b0)
Force lane realignment in Link status monitor
For TI use only
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