TLK10031 Datasheet, PDF (102/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
www.ti.com
7.5.3.19 KR_FEC_CONTROL (register = 0x00AB) (default = 0x0000) (device address: 0x01)
Figure 7-106. KR_FEC_CONTROL Register
15
14
13
12
11
10
RESERVED
RW
7
6
5
4
3
2
RESERVED
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
9
1
KR_FEC_ERR
_INDEN
(R)
RW
8
0
KR_FEC_EN
(R)
RW
Bit Field
15:2 RESERVED
1 KR_FEC_ERR_IND_EN
(R)
0 KR_FEC_EN
(R)
Table 7-88. KR_FEC_CONTROL Field Descriptions
Type
RW
RW
RW
Reset
Description
For TI use only. Always reads 0.
1 = Enable FEC decoder to indicate errors to PCS
0 = Disable FEC decoder error indication to PCS (Default 1’b0)
1 = Enable 10GBASE-R FEC function
0 = Disable 10GBASE-R FEC function (Default 1’b0)
7.5.3.20 KR_FEC_C_COUNT_1 (register = 0x00AC) (default = 0x0000) (device address: 0x01)
Figure 7-107. KR_FEC_C_COUNT_1 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
KR_FEC_C_COUNT[15:0]
(R)
COR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-89. KR_FEC_C_COUNT_1⁽¹⁾ Field Descriptions
Bit Field
15:0 KR_FEC_C_COUNT[15:0]
(R)
Type Reset Description
COR
Lower 16 bits of FEC corrected blocks counter
(1) To get correct 32 bit counter value of KR_FEC_C_COUNT, Register 01.00AC should be read first followed by Register 01.00AD
7.5.3.21 KR_FEC_C_COUNT_2 (register = 0x00AD) (default = 0x0000) (device address: 0x01)
Figure 7-108. KR_FEC_C_COUNT_2 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
KR_FEC_C_COUNT[31:16]
(R)
COR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-90. KR_FEC_C_COUNT_2 Field Descriptions
Bit Field
15:0 KR_FEC_C_COUNT[31:16]
(R)
Type Reset Description
COR
Upper 16 bits of FEC corrected blocks counter
102 Detailed Description
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