TLK10031 Datasheet, PDF (59/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
7.5.2.4 HS_SERDES_CONTROL_2 (register: 0x0003) (default: 0xA848) (device address: 0x1E)
Figure 7-44. HS_SERDES_CONTROL_2 Register
15
14
13
12
11
10
9
8
HS_SWING[3:0]
(RXG)
HS_ENTX
(RXG)
HS_EQHLD
(RXG)
HS_RATE_TX [1:0]
(RXG)
R/W
R/W
R/W
R/W
7
6
5
4
HS_AGCCTRL[1:0]
(RXG
HS_AZCAL[1:0]
(RXG)
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
HS_ENRX
(RXG)
R/W
2
1
0
HS_RATE_RX [2:0]
(RXG)
R/W
Bit
15:12
11
Field
HS_SWING[3:0]
(RXG)
HS_ENTX
(RXG)
10 HS_EQHLD
(RXG)
9:8 HS_RATE_TX [1:0]
(RXG)
7:6 HS_AGCCTRL[1:0]
(RXG)
5:4 HS_AZCAL[1:0]
(RXG)
3
HS_ENRX
(RXG)
2:0 HS_RATE_RX [2:0]
(RXG)
Table 7-16. HS_SERDES_CONTROL_2 Field Description
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
Transmitter Output swing control for HS Serdes. (Default 4’b1010)
Refer Table 7-17.
HS Serdes transmitter enable control. HS Serdes transmitter is automatically disabled
when PD_TRXx_N is asserted LOW or when register bit 1E.0001 bit 15 is set HIGH.
0 = Disables HS serdes transmitter
1 = Enables HS serdes transmitter (Default 1’b1)
HSRX Equalizer hold control.
0 = Normal operation (Default 1’b0)
1 = Holds equalizer and long tail correction in its current state
HS Serdes TX rate settings.
00 = Full rate (Default 2’b00)
01 = Half rate
10 = Quarter rate
11 = Eighth rate
Adaptive gain control loop.
00 = Attenuator will not change after lock has been achieved, even if AGC becomes
unlocked
01 = Attenuator will not change when in lock state, but could change when AGC becomes
unlocked (Default 2’b01)
10 = Force the attenuator off
11 = Force the attenuator on
Auto zero calibration.
00 = Auto zero calibration initiated when receiver is enabled (Default 2’b00)
01 = Auto zero calibration disabled
10 = Forced with automatic update.
11 = Forced without automatic update
HS Serdes receiver enable control.
HS Serdes receiver is automatically disabled when PD_TRXx_N is asserted LOW or when
register bit 1E.0001 bit 15 is set HIGH.
0 = Disables HS serdes receiver
1 = Enables HS serdes receiver (Default 1’b1)
HS Serdes RX rate settings. This setting is automatically controlled and value set through
these register bits is ignored unless REFCLK_FREQ_SEL_1 or related OVERRIDE bit is
set.
000 = Full rate (Default 3’b000)
001 = Half rate
110 = Quarter rate
111 = Eighth rate
001 = Reserved
01x = Reserved
100 = Reserved
Copyright © 2015, Texas Instruments Incorporated
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