TLK10031 Datasheet, PDF (55/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
7.5 Register Maps
7.5.1 Register Bit Definitions
7.5.1.1 RW: Read-Write
User can write 0 or 1 to this register bit. Reading this register bit returns the same value that has been
written.
7.5.1.2 RW/SC: Read-Write Self-Clearing
User can write 0 or 1 to this register bit. Writing a "1" to this register creates a high pulse. Reading this
register bit always returns 0.
7.5.1.3 RO: Read-Only
This register can only be read. Writing to this register bit has no effect. Reading from this register bit
returns its current value.
7.5.1.4 RO/LH: Read-Only Latched High
This register can only be read. Writing to this register bit has no effect. Reading a "1" from this register bit
indicates that either the condition is occurring or it has occurred since the last time it was read. Reading a
"0" from this register bit indicates that the condition is not occurring presently, and it has not occurred
since the last time the register was read. A latched high register, when read high, should be read again to
distinguish if a condition occurred previously or is still occurring. If it occurred previously, the second read
will read low. If it is still occurring, the second read will read high. Reading this register bit automatically
resets its value to 0.
7.5.1.5 RO/LL: Read-Only Latched Low
This register can only be read. Writing to this register bit has no effect. Reading a "0" from this register bit
indicates that either the condition is occurring or it has occurred since the last time it was read. Reading a
"1" from this register bit indicates that the condition is not occurring presently, and it has not occurred
since the last time the register was read. A latched low register, when read low, should be read again to
distinguish if a condition occurred previously or is still occurring. If it occurred previously, the second read
will read high. If it is still occurring, the second read will read low. Reading this register bit automatically
sets its value to 1.
7.5.1.6 COR: Clear-On-Read
This register can only be read. Writing to this register bit has no effect. Reading from this register bit
returns its current value, then resets its value to 0. Counter value freezes at Max.
Following code letters in Name field of each control/status register bit(s) indicate the mode that they are
applicable/valid.
R = Indicates control/status bit(s) valid in 10GKR mode
X = Indicates control/status bit(s) valid in 1GKX mode
G = Indicates control/status bit(s) valid in 10G general purpose serdes mode
7.5.2 Vendor Specific Device Registers
Below registers can be accessed directly through Clause 22 and Clause 45. In Clause 45 mode, these
registers can be accessed by setting device address field to 0x1E (DA[4:0] = 5’b11110). In Clause 22
mode, these registers can be accessed by setting 5 bit register address field to same value as 5 LSB bits
of Register Address field specified for each register. For example, 16 bit register address 0x001C in
clause 45 mode can be accessed by setting register address field to 5’h1C in clause 22 mode.
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