TLK10031 Datasheet, PDF (107/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
7.5.3.28 KR_VS_CTC_ERR_CODE_LN1 (register = 0x8006) (default =0x0000)
(device address: 0x01)
Figure 7-115. KR_VS_CTC_ERR_CODE_LN1 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
KR_CTC_ERR_CODE_LN1
(R)
RESERVED
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-97. KR_VS_CTC_ERR_CODE_LN1 Field Descriptions
Bit Name
15:7 KR_CTC_ERR_CODE_LN1
(R)
6:0 RESERVED
Type
RW
Reset
RW
Description
Applicable in 10G-KR mode only. XGMII code to be transmitted in case of error
condition. This applies to both TX and RX data paths. The msb is the control bit;
remaining 8 bits constitute the error code. The default value for lane 1 corresponds to
8’h00 with the control bit being 1’b0. The default values for lanes 0~3 correspond to
||LF||
For TI use only. Always reads 0.
7.5.3.29 KR_VS_CTC_ERR_CODE_LN2 (register = 0x8007) (default = 0x0000)
(device address: 0x01)
Figure 7-116. KR_VS_CTC_ERR_CODE_LN2 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
KR_CTC_ERR_CODE_LN2
(R)
RESERVED
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit(s)
15:7
6:0
Table 7-98. KR_VS_CTC_ERR_CODE_LN2 Field Descriptions
Name
KR_CTC_ERR_CODE_LN2
(R)
RESERVED
Type
RW
RW
Reset
Description
Applicable in 10G-KR mode only. XGMII code to be transmitted in case of error
condition. This applies to both TX and RX data paths. The msb is the control bit;
remaining 8 bits constitute the error code. The default value for lane 2 corresponds to
8’h00 with the control bit being 1’b0. The default values for lanes 0~3 correspond to
||LF||
For TI use only. Always reads 0.
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Detailed Description 107