TLK10031 Datasheet, PDF (3/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
3 Description (continued)
While operating in the 10GBASE-KR mode, the TLK10031 performs serialization of the 8B/10B encoded
XAUI data stream presented on its low speed (LS) side data inputs. The serialized 8B/10B encoded data
is presented on the high speed (HS) side outputs in 64B/66B encoding format. Likewise, the TLK10031
performs deserialization of 64B/66B encoded data streams presented on its high speed side data inputs.
The deserialized 64B/66B data is presented in XAUI 8B/10B format on the low speed side outputs. Link
Training is supported in this mode as well as Forward Error Correction (FEC) for extended length
applications.
While operating in the General Purpose SERDES mode, the TLK10031 performs 2:1 and 4:1 serialization
of the 8B/10B encoded data streams presented on its low speed (LS) side data inputs. The serialized
8B/10B encoded data is presented on the high speed (HS) side outputs. Likewise, the TLK10031 performs
1:2 and 1:4 deserialization of 8B/10B encoded data streams presented on its high speed side data inputs.
The deserialized 8B/10B encoded data is presented on the low speed side outputs. Depending on the
serialization/deserialization ratio, the low speed side data rate can range from 0.5 Gbps to 5 Gbps and the
high speed side data rate can range from 1 Gbps to 10 Gbps. 1:1 retime mode is also supported but
limited to 1 Gbps to 5 Gbps rates.
The TLK10031 also supports 1G-KX (1.25 Gbps) mode with PCS (CTC) capabilities. This mode can be
enabled via software provisioning or via auto negotiation. If software provisioning is used, data rates up to
3.125 Gbps are supported.
The TLK10031 features a built-in crosspoint switch, allowing for redundant outputs and easy re-routing of
data. Each output port (either high speed or low speed) can be configured to output data coming from any
of the device’s input ports. The switching can be initiated through either a hardware pin or through
software control, and can be configured to occur either immediately or after the end of the current packet.
This allows for switching between data sources without packet corruption.
Both low speed and high speed side data inputs and outputs are of differential current mode logic (CML)
type with integrated termination resistors.
The TLK10031 provides flexible clocking schemes to support various operations. They include the support
for clocking with an externally-jitter-cleaned clock recovered from the high speed side. The device is also
capable of performing clock tolerance compensation (CTC) in 10GBASE-KR and 1GBASE-KX modes,
allowing for asynchronous clocking.
The TLK10031 provides low speed side and high speed side loopback modes for self-test and system
diagnostic purposes.
The TLK10031 has built-in pattern generators and verifiers to help in system tests. The device supports
generation and verification of various PRBS, High-/Low-/Mixed-Frequency, CRPAT long/short, CJPAT,
and KR pseudo-random test patterns and square wave generation. The types of patterns supported on the
low speed and high speed side are dependent on the operational mode chosen.
The TLK10031 has an integrated loss of signal (LOS) detection function on both high speed and low
speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS
assert threshold.
The low speed side of the TLK10031 is ideal for interfacing with an FPGA, ASIC, MAC, or network
processor capable of handling lower-rate serial data streams. The high speed side is ideal for interfacing
with remote systems through optical fibers, electrical cables, or backplane interfaces. The device supports
operation with SFP and SFP+ optical modules, as well as 10GBASE-KR compatible backplane systems.
Copyright © 2015, Texas Instruments Incorporated
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Description (continued)
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