TLK10031 Datasheet, PDF (5/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
Pin Description - Signal Pins (continued)
PIN
NAME
NO.
I/O
TYPE
DESCRIPTION
LS_OK_OUT_A
D9
Output LVCMOS
1.5V/1.8V
VDDO
40Ω Driver
Transmit Lane Alignment Status Indicator.
Lane alignment status signal sent to a Lane Alignment Master on the link partner device.
Valid in 10G General Purpose Serdes Mode.
LS_OK_OUT_A = 0: Link partner transmit lanes not aligned.
LS_OK_OUT_A = 1: Link partner transmit lanes aligned.
PDTRXA_N
Transceiver Power Down.
A8
Input LVCMOS
1.5V/1.8V VDDO0
When this pin is held low (asserted), the channel is placed in power down mode. When
deasserted, the channel operates normally. After deassertion, a software data path reset
should be issued through the MDIO interface.
RESERVED PINS
RSV[7:0]
L12, K12,
K8, H12,
H9, G12,
A10, A9
Reserved.
It should be left unconnected in the device application.
REFERENCE CLOCKS, OUTPUT CLOCKS, AND CONTROL AND MONITORING SIGNALS
REFCLK0P/N
M10
M11
Input
LVDS/ LVPECL
DVDD
Reference Clock Input Zero. This differential input is a clock signal used as a reference
to channel A. The reference clock selection is done through MDIO. This input signal must
be AC coupled. If unused, REFCLK0P/N should be pulled down to GND through a shared
100 Ω resistor.
REFCLK1P/N
K9
K10
Input
LVDS/ LVPECL
DVDD
Reference Clock Input One. This differential input is a clock signal used as a reference
to channel A. The reference clock selection is done through MDIO. This input signal must
be AC coupled. If unused, REFCLK1P/N should be pulled down to GND through a shared
100 Ω resistor.
CLKOUTAP/N
Channel Output Clock. By default, this outputs is enabled, and outputs the high speed
side recovered byte clock (high speed line rate divided by 16 or 20). Optionally, they can
be configured to output the VCO clock divided by 2. (Note: for full rates, VCO/2 pre-
C9
C10
Output
CML
DVDD
divided clocks will be equivalent to the line rate divided by 8; for sub-rates, VCO/2 pre-
divided clocks will be equivalent to the line rate divided by 4).
These CML outputs must be AC coupled.
During device reset (RESET_N asserted low), pin-based power down (PDTRXA_N
asserted low), or register-based power down, these pins are floating.
PRBSEN
Enable PRBS: When this pin is asserted high, the internal PRBS generator and verifier
Input
circuits are enabled on both transmit and receive data paths on high speed and low speed
B9
LVCMOS 1.5V/1.8V _sides.
VDDO0
The PRBS 2⁷-1 pattern is selected by default, and can be changed through MDIO.
PRBS_PASS
Receive PRBS Error Free (Pass) Indicator.
When PRBS test is enabled (PRBSEN=1):
PRBS_PASS = 1 indicates that PRBS pattern reception is error free.
J9
Output
LVCMOS 1.5V/1.8V
VDDO1
PRBS_PASS = 0 indicates that a PRBS error is detected. The high speed or low speed
side, and lane (for low speed side) that this signal refers to is chosen through MDIO.
During device reset (RESET_N asserted low) this pin is driven high.
40Ω Driver
During pin based power down (PDTRXA_N asserted low), this pin is floating.
During register based power down, this pin is floating.
It is highly recommended that PRBS_PASS be brought to easily accessible point on the
application board (header), in the event that debug is required.
Input
MDIO Select. Used to select Clause 22 (=1) or Clause 45 (=0) operation. Note that
ST
M9
LVCMOS 1.5V/1.8V ^{selecting clause 22 will impact mode availability. See MODE_SEL.}
VDDO[1:0]
A hard or soft reset must be applied after a change of state occurs on this input signal.
MODE_SEL
H10
Input LVCMOS
Device Operating Mode Select.
1.5V/1.8V VDDO[1:0] Used together with ST pin to select device operating mode. See Table 7-2 for details.
MDIO Port Address. Used to select the MDIO port address.
PRTAD[4:0]
PRTAD[4:1] selects the MDIO port address. The TLK10031 has one MDIO port
M8
addresses. Selecting a unique PRTAD[4:1] per TLK10031 device allows 16 TLK10031
J6
L9
G9
Input LVCMOS
1.5V/1.8V VDDO[1:0]
devices per MDIO bus.
The TLK10031 responds if the 4 MSB’s of the port address field on MDIO protocol
(PA[4:1]) matches PRTAD[4:1], and PA[0] = 0.
E10
PRTAD0 is not needed for port addressing, but can be used as a general purpose input
pin to control the switching function or the stopwatch latency measurement. If these
functions are not needed, PRTAD0 should be grounded on the application board.
RESET_N
H5
Input LVCMOS
1.5V/1.8V VDDO01
Low True Device Reset. RESET_N must be held asserted (low logic level) for at least 10
µs after device power stabilization.
MDC
Input LVCMOS
MDIO Clock Input. Clock input for the MDIO interface.
J8
with Hysteresis
Note that an external pullup is generally not required on MDC except if driven by an open-
1.5V/1.8V VDDO1 drain/open-collector clock source.
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Pin Configuration and Functions
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