TLK10031 Datasheet, PDF (64/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
www.ti.com
7.5.2.7 LS_SERDES_CONTROL_1 (register: 0x0006) (default: 0xF115) (device address: 0x1E)
Figure 7-47. LS_SERDES_CONTROL_1 Register
15
14
13
12
LS_LN_CFG_EN[3:0]
(RXG)
R/W
11
10
RESERVED
R/W
9
8
LS_LOOP_BANDWIDTH[1:0]
(RXG)
R/W
7
6
5
4
3
2
1
0
RESERVED
LS_ENPLL
(RXG)
LS_MPY[3:0]
(RXG)
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-24. LS_SERDES_CONTROL_1 Field Description
Bit
15:12
Field
LS_LN_CFG_EN[3:0]
(RXG)
11:10
9:8
RESERVED
LS_LOOP_BANDWIDTH[1:0]
(RXG)
7:5 RESERVED
4 LS_ENPLL
(RXG)
3:0 LS_MPY[3:0]
(RXG)
Type
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
Configuration control for LS Serdes Lane settings (Default 4’b1111)
[3] corresponds to LN3, [2] corresponds to LN2
[1] corresponds to LN1, [0] corresponds to LN0
0 = Writes to LS_SERDES_CONTROL_2 and LS_SERDES_CONTROL_3 and
LS_CH_CONTROL_1 control registers do not affect respective LS Serdes lane
1 = Writes to LS_SERDES_CONTROL_2 and LS_SERDES_CONTROL_3 and
LS_CH_CONTROL_1 control registers affect respective LS Serdes lane
For example, if subsequent writes to LS_SERDES_CONTROL_2 and
LS_SERDES_CONTROL_3 and LS_CH_CONTROL_1 registers need to affect the settings in
Lanes 0 and 1, LS_LN_CFG_EN[3:0] should be set to 4’b0011
Read values in LS_SERDES_CONTROL_2 and LS_SERDES_CONTROL_3 and
LS_CH_CONTROL_1 reflect the settings value for Lane selected through
LS_LN_CFG_EN[3:0].
To read Lane 0 settings, LS_LN_CFG_EN[3:0] should be set to 4’b0001
To read Lane 1 settings, LS_LN_CFG_EN[3:0] should be set to 4’b0010
To read Lane 2 settings, LS_LN_CFG_EN[3:0] should be set to 4’b0100
To read Lane 3 settings, LS_LN_CFG_EN[3:0] should be set to 4’b1000
Read values of LS_SERDES_CONTROL_2 and LS_SERDES_CONTROL_3 and
LS_CH_CONTROL_1 registers are not valid for any other LS_LN_CFG_EN[3:0] combination
For TI use only (Default 2’b00)
LS Serdes PLL Loop Bandwidth settings
00 = Reserved
01 = Applicable when external JC_PLL is NOT used (Default 2’b01)
10 = Applicable when external JC_PLL is used
11 = Reserved
For TI use only (Default 3’b000)
LS Serdes PLL enable control. LS Serdes PLL is automatically disabled when PD_TRXx_N
is asserted LOW or when register bit 1E.0001 bit 15 is set HIGH.
0 = Disables PLL in LS serdes
1 = Enables PLL in LS serdes (Default 1’b1)
LS Serdes PLL multiplier setting (Default 4’b0101).
Refer 10GKR supported rates for valid PLL Multiplier values.
Refer to Table 7-25.
Value
0000
0001
0010
0011
0100
0101
0110
0111
Table 7-25. LS PLL Multiplier Control
LS_MPY[3:0]
PLL Multiplier factor
4x
5x
6x
Reserved
8x
10x
12x
12.5x
Value
1000
1001
1010
1011
1100
1101
1110
1111
LS_MPY[3:0]
PLL Multiplier factor
15x
20x
25x
Reserved
Reserved
50x
65x
Reserved
64
Detailed Description
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