TLK10031 Datasheet, PDF (4/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
www.ti.com
4 Pin Configuration and Functions
A 13-mm x 13-mm, 144-pin PBGA package with a ball pitch of 1 mm is used.
4.1 Pin Configurations
1
A
INA1P
B
INIA1N
C
VSS
D
INA3P
E
INA3N
F
VSS
G
VSS
H
VSS
J
VSS
K
VSS
L
VSS
M
VSS
2
VSS
INA2P
INA2N
VDDA_LS
VSS
VDDA_LS
VDDA_LS
VSS
VDDA_LS
VSS
VSS
VSS
3
INA0N
VSS
VDDRA_LS
VSS
OUTA3N
OUTA3P
VSS
VSS
VSS
VDDRA_LS
VSS
VSS
4
INA0P
VSS
OUTA2P
AMUX1
VSS
VDDT_LS
VDDT_LS
VSS
GPI1
VSS
VSS
VSS
TLK10031 Pinout
5
6
7
VSS
OUTA0P
OUTA0N
OUTA1P
OUTA1N
VSS
OUTA2N
VSS
VDDO0
VSS
TDO
VPP
TRST_N
VDDD
DVDD
VSS
VDDD
DVDD
VSS
DVDD
VSS
RESE_TN
VDDD
DVDD
VSS
PRTAD3
MDIO
VSS
VSS
VDDO1
VSS
VSS
VSS
VSS
VSS
VSS
8
PDTRXA_N
TMS
TDI
TCK
VDDD
VSS
DVDD
VDDD
MDC
RSV5
GPI2
PRTAD4
9
RSV0
PRBSEN
CLKOUTAP
LS_OK_OUT_A
LOSA
VDDT_HS
PRTAD1
RSV3
PRBS_PASS
REFCLK1P
PRTAD2
ST
10
RSV1
LS_OK_IN_A
CLKOUTAN
VSS
PRTAD0
VSS
VDDA_HS
MODE_SEL
GPI0
REFCLK1N
TESTEN
REFCLK0P
11
VSS
VSS
AMUX0
VSS
VDDRA_HS
VDDA_HS
VSS
VSS
VDDRA_HS
VSS
VSS
REFCLK0N
12
HSRXAN
HSRXAP
VSS
HSTXAP
HSTXAN
VSS
RSV2
RSV4
VSS
RSV6
RSV7
VSS
4.2 Pin Functions
PIN
NAME
HSTXAP
HSTXAN
HSRXAP
HSRXAN
INA[3:0]P/N
OUTA[3:0]P/N
NO.
D12
E12
B12
A12
D1/E1
B2/C2
A1/B1
A4/A3
F3/E3
C4/C5
B5/B6
A6/A7
LOSA
E9
LS_OK_IN_A
B10
Pin Description - Signal Pins
I/O
TYPE
Output
CML VDDA_HS
Input
CML VDDA_HS
DESCRIPTION
High Speed Transmit Output. HSTXAP and HSTXAN comprise the high speed side
transmit direction differential serial output signal. During device reset (RESET_N asserted
low) these pins are driven differential zero. These CML outputs must be AC coupled.
High Speed Receive Input. HSRXAP and HSRXAN comprise the high speed side
receive direction differential serial input signal. These CML input signals must be AC
coupled.
Input
CML VDDA_LS
Low Speed Inputs. INAP and INAN comprise the low speed side transmit direction
differential input signals. These signals must be AC coupled.
Output
CML VDDA_LS
Output LVCMOS
1.5V/1.8V
VDDO0
40Ω Driver
Input LVCMOS
1.5V/1.8V
VDDO0
Low Speed Outputs. OUTAP and OUTAN comprise the low speed side receive direction
differential output signals. During device reset (RESET_N asserted low) these pins are
driven differential zero. These signals must be AC coupled.
Receive Loss Of Signal (LOS) Indicator.
LOS = 0: Signal detected.
LOS = 1: Loss of signal.
Loss of signal detection is based on the input signal level. When HSRXAP/N has a
differential input signal swing of ≤75 mV_pp, LOSA is asserted (if enabled). If the input
signal is greater than 150 mV_pp, LOSA is deasserted. Outside of these ranges, the LOS
indication is undefined.
Other functions can be observed on LOSA real-time, configured via MDIO
During device reset (RESET_N asserted low) this pin is driven low. During pin based
power down (PDTRXA_N asserted low), this pin is floating. During register based power
down, this pin is floating.
It is highly recommended that LOSA be brought to an easily accessible point on the
application board (header) in the event that debug is required.
Receive Lane Alignment Status Indicator.
Lane alignment status signal received from a Lane Alignment Slave on the link partner
device. Valid in 10G General Purpose Serdes Mode.
LS_OK_IN_A = 0: Link partner receive lanes not aligned.
LS_OK_IN_A = 1: Link partner receive lanes aligned
4
Pin Configuration and Functions
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