TLK10031 Datasheet, PDF (57/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
7.5.2.2 CHANNEL_CONTROL_1 (register: 0x0001) (default: 0x0B00) (device address: 0x1E)⁽¹⁾
(1) This global register is channel independent.
Figure 7-42. CHANNEL_CONTROL_1 Register
15
POWERDOWN
(RXG)
R/W
14
LT_TRAINING_
CONTROL
(XG)
R/W
13
10G_RX_MOD
E_SEL
(G)
R/W
12
10G_TX_MOD
E_SEL
(G)
R/W
11
SW_PCS_SEL
(RX)
R/W
10
SW_DEV_MOD
E_SEL
(RXG)
R/W
9
10G_RX_DEM
UX_SEL
(G)
R/W
8
10G_TX_MUX_
SEL
(G)
R/W
7
6
5
4
3
RESERVED
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
2
1
0
REFCLK_SW_ LS_REFCLK_S
SEL
EL
(RXG)
(RXG)
R/W
R/W
Bit Field
15 POWERDOWN
(RXG)
14 LT_TRAINING_CONTROL
(XG)
13 10G_RX_MODE_SEL
(G)
12 10G_TX_MODE_SEL
(G)
11 SW_PCS_SEL
(RX)
10 SW_DEV_MODE_SEL
(RXG)
9 10G_RX_DEMUX_SEL
(G)
8 10G_TX_MUX_SEL
(G)
7:2 RESERVED
1 REFCLK_SW_SEL
(RXG)
0 LS_REFCLK_SEL
(RXG)
Table 7-13. CHANNEL_CONTROL_1 Field Description
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/O
R/W
R/W
Reset
Description
Setting this bit high powers down entire data path with exception that MDIO interface stays
active.
0 = Normal operation (Default 1’b0)
1 = Power Down mode is enabled.
Link training control. Valid in 10G and 1GKX modes only.
0 = Link training disabled(Default 1’b0)
1 = Link training enable control dependent on LT_TRAINING_ENABLE (1E.0036 bit 1).
RX mode selection. Valid in 10G only.
0 = RX mode dependent upon RX_DEMUX_SEL(Default 1’b0)
1 = Enables 1 to 1 mode on receive channel.
TX mode selection Valid in 10G only.
1 = TX mode dependent upon TX_MUX_SEL (Default 1’b0)
0 = Enables 1 to 1 mode on transmit channel.
Applicable in Clause 45 mode only. Valid only when MODE_SEL pin is 0, AN_ENABLE
(07.0000 bit 12) is 0 and SW_DEV_MODE_SEL (1E.0001 bit 10) is 0.
0 = Set device to 10G-KR mode(Default 1’b1)
1 = Set device to 1G-KX mode
Valid only when MODE_SEL pin is 0
0 = Device set to 10G mode
1 = In clause 45 mode, device mode is set using Auto negotiation. In clause 22 mode, device
set to 1G-KX mode(Default 1’b0)
RX De-Mux selection control for lane de-serialization on receive channel. Valid in 10G and
when 10G_RX_MODE_SEL (1E.0001 bit 13) is LOW
0 = 1 to 2
1 = 1 to 4 (Default 1’b1)
TX Mux selection control for lane serialization on transmit channel. Valid in 10G and when
10G_TX_MODE_SEL (1E.0001 bit 12) is LOW
1 = 2 to 1
0 = 4 to 1 (Default 1’b1)
For TI use only
HS Reference clock selection.
1 = Selects REFCLK_0_P/N as clock reference to HS side serdes macro(Default 1’b0)
0 = Selects REFCLK_1_P/N as clock reference to HS side serdes macro
LS Reference clock selection.
0 = LS side serdes macro reference clock is same as HS side serdes reference clock (E.g. If
REFCLK_0_P/N is selected as HS side serdes macro reference clock, REFCLK_0_P/N is
selected as LS side serdes macro reference clock and vice versa) (Default 1’b0)
1 = Alternate reference clock is selected as clock reference to LS side serdes macro (E.g. If
REFCLK_0_P/N is selected as HS side serdes macro reference clock, REFCLK_1_P/N is
selected as LS side serdes macro reference clock and vice versa)
Copyright © 2015, Texas Instruments Incorporated
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