TLK10031 Datasheet, PDF (22/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
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7.3.4 8B/10B Encoder
Embedded-clock serial interfaces require a method of encoding to ensure sufficient transition density for
the receiving CDR to acquire and maintain lock. The encoding scheme also maintains the signal DC
balance by keeping the number of ones and zeros balanced which allows for AC coupled data
transmission. The TLK10031 uses the 8B/10B encoding algorithm that is used by the 10 Gbps and 1 Gbps
Ethernet and Fibre Channel standards. This provides good transition density for clock recovery and
improves error checking.
The 8B/10B encoder converts each 8-bit wide data to a 10-bit wide encoded data character to improve its
transition density. This transmission code includes /D/ characters, used for transmitting data, and /K/
characters, used for transmitting protocol information. Each /K/ or /D/ character code word can also have
both a positive and a negative disparity version. The disparity of a code word is selected by the encoder to
balance the running disparity of the serialized data stream.
7.3.5 8B/10B Decoder
Once the Channel Synchronization block has identified the byte boundaries from the received serial data
stream, the 8B/10B decoder converts 10-bit 8B/10B-encoded characters into their respective 8-bit formats.
When a code word error or running disparity error is detected in the decoded data, the error is reported in
the status register (1E.000F) and the LOS pin is asserted (depending on the LOS overlay selection).
7.3.6 64B/66B Encoder/Scrambler
To facilitate the transmission of data received from the media access control (MAC) layer, the TLK10031
encodes data received from the MAC using the 64B/66B encoding algorithm defined in the IEEE802.3-
2008 standard. The TLK10031 takes two consecutive transfers from the XAUI interface and encodes them
into a 66-bit code word. The information from the two XAUI transfers includes 64 bits of data and 8 bits of
control information after 8B/10B decoding.
If the 64B/66B encoder detects an invalid packet format from the XAUI interface, it replaces erroneous
information with appropriately-encoded error information. The resulting 66-bit code word is then sent on to
the transmit gearbox.
The encoding process implemented in the TLK10031 includes two steps:
1. an encoding step, which converts the 72 bits of data (8 data bytes plus 8 control-code indicators)
received from the transmit CTC FIFO into a 66-bit code word
2. a scrambling step, which scrambles 64 bits of encoded data using the scrambler polynomial x⁵⁸+x³⁹+1.
The 66 bits created by the encoder consists of 64 bits of data and a 2-bit synchronization field
consisting of either 01 or 10. Only the 64 bits of data are scrambled, leaving the two synchronization
bits unmodified. The two synchronization bits allow the receive gearbox to obtain frame alignment and,
in addition, ensure an edge transition of at least once in 66 bits of data. The encoding process allows a
limited amount of control information to be sent in-line with the data.
7.3.7 Forward Error Correction
Optionally enabled, Forward Error Correction (FEC) follows the IEEE 802.3-2008 standard, and is able to
correct a burst errors up to 11 bits. In the TX data path, the FEC logic resides between the scrambler and
gearbox. In the RX datapath, FEC resides between the gearbox and descrambler. Frame alignment is
handled inside the RX FEC block during FEC operation, and the RX gearbox sync header alignment is
bypassed. Because latency is increased in both the TX and RX data paths with FEC enabled, it is
disabled by default and must be enabled through MDIO programming. Note that FEC by nature will add
latency due to frame storage.
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