TLK10031 Datasheet, PDF (29/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
Table 7-3. Specific Line Rate and Reference Clock Selection for the 1GBASE-KX Mode
LOW SPEED SIDE
HIGH SPEED SIDE
Line Rate
(Mbps)
3125 ⁽²⁾
3125 ⁽²⁾
1250
SERDES PLL
Multiplier
10
5
10
Rate
Full
Full
Half
REFCLKP/N
(MHz)
156.25
312.5
125 ⁽²⁾
Line Rate
(Mbps⁽¹⁾ )
3125 ⁽²⁾
3125 ⁽²⁾
1250
SERDES PLL
Multiplier
10
5
20
Rate
Full
Full
Quarter
REFCLKP/N
(MHz)
156.25
312.5
125 ⁽²⁾
1250
8
Half
156.25
1250
16
Quarter
156.25
1250
8
Quarter
312.5
1250
8
Quarter
312.5
(1) High Speed Side SERDES runs at 2x effective data rate.
(2) Manual mode only, as auto negotiation does not support 125Mhz REFCLK or line rate of 3125Mbps. To disable automatic setting of PLL
and rate modes, write 1'b1 to bit 13 of register 0x1E.001D.
7.4.2.5 1GBASE-KX Mode Latency
The latency through the TLK10031 in 1G-KX mode is as shown in Figure 7-9. Note that the latency ranges
shown indicate static rather than dynamic latency variance, i.e., the range of possible latencies when the
serial link is initially established. During normal operation, the latency through the device is fixed.
Figure 7-9. 1G-KX Mode Latency
Copyright © 2015, Texas Instruments Incorporated
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