TLK10031 Datasheet, PDF (43/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
7.4.16.2 High Speed Receiver
The high speed receiver is differential CML with internal termination resistors. The receiver requires AC
coupling. The termination impedances of the receivers are configured as 100 Ω with the center tap weakly
tied to 0.7×VDDT, and a capacitor is used to create an AC ground (see Figure 7-17).
TLK10031 serial receivers incorporate adaptive equalizers. This circuit compensates for channel insertion
loss by amplifying the high frequency components of the signal, reducing inter-symbol interference.
Equalization can be enabled or disabled per register settings. Both feed-forward equalization (FFE) and
decision feedback equalization (DFE) are used to minimize the pre-cursor and post-cursor components
(respectively) of intersymbol interference.
7.4.16.3 Loss of Signal Output Generation (LOS)
Loss of input signal detection is based on the voltage level of each serial input signal INA*P/N,
HSRXAP/N. When LOS indication is enabled and the channel's differential serial receive input level is <
75 mVpp, the channel's respective LOS indicator (LOSA) are asserted (high true). If the input signal is
>150 mVpp, the LOS indicator will be deasserted (low false). Outside of these ranges, the LOS indicator is
undefined. The LOS indicators can also directly be read through the MDIO interface.
The following additional critical status conditions can be combined with the loss of signal condition
enabling additional real-time status signal visibility on the LOSA output:
1. Loss of Channel Synchronization Status – Logically OR’d with LOS condition(s) when enabled. Loss of
channel synchronization can be optionally logically OR’d (disabled by default) with the internally
generated LOS condition.
2. Loss of PLL Lock Status on LS and HS sides – Logically OR’d with LOS condition(s) when enabled.
The internal PLL loss of lock status bit is optionally OR’d (disabled by default) with the other internally
generated loss of signal conditions.
3. Receive 8B/10B Decode Error (Invalid Code Word or Running Disparity Error) – Logically OR’d with
LOS condition(s) when enabled. The occurrence of an 8B/10B decode error (invalid code word or
disparity error) is optionally OR’d (disabled by default) with the other internally generated loss of signal
conditions.
4. AGCLOCK (Active Gain Control Currently Locked) – Inverted and Logically OR’d with LOS condition(s)
when enabled. HS RX SERDES adaptive gain control unlocked indication is optionally OR’d (disabled
by default) with the other internally generated loss of signal conditions.
5. AZDONE (Auto Zero Calibration Done) - Inverted and Logically OR’d with LOS conditions(s) when
enabled. HS RX SERDES auto-zero not done indication is optionally OR’d (disabled by default) with
the other internally generated loss of signal conditions.
Refer to Figure 7-18, which shows the detailed implementation of the LOSA signal along with the
associated MDIO control registers for the General Purpose SERDES mode. More details about LOS
settings including configurations related to the 10GBASE-KR mode can be found in the Programmers
Reference section.
Copyright © 2015, Texas Instruments Incorporated
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