TLK10031 Datasheet, PDF (74/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
www.ti.com
7.5.2.17 CHANNEL_STATUS_1 (register: 0x000F) (default: 0x0000) (device address: 0x1E)
Figure 7-57. CHANNEL_STATUS_1 Register
15
HS_TP_STATU
S
(XG)
R
14
LS_ALIGN_ST
ATUS
(RXG)
R
13
HS_LOS
(RXG)
R
12
HS_AZ_DONE
(RXG)
R
11
HS_AGC_LOC
KED
(RXG)
R
10
HS_CHANNEL
_SYNC
(RXG)
R
9
RESERVED
R
8
HS_DECODE_I
NVALID
(RXG)
R
7
6
5
4
TX_FIFO_UND TX_FIFO_OVE RX_FIFO_UND RX_FIFO_OVE
ERFLOW
RFLOW
ERFLOW
RFLOW
(RG)
(RXG)
(RG)
(RXG)
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
RX_LS_OK
(G)
R
2
TX_LS_OK
(G)
R
1
0
LS_PLL_LOCK HS_PLL_LOCK
(RXG)
(RXG)
R
R
Bit Field
15 HS_TP_STATUS
(XG)
14 LS_ALIGN_STATUS
(RXG)
13 HS_LOS
(RXG)
12 HS_AZ_DONE
(RXG)
11 HS_AGC_LOCKED
(RXG)
10 HS_CHANNEL_SYNC
(RXG)
9 RESERVED
8 HS_DECODE_INVALID
(RXG)
7 TX_FIFO_UNDERFLOW
(RG)
6 TX_FIFO_OVERFLOW
(RXG)
5 RX_FIFO_UNDERFLOW
(RG)
4 RX_FIFO_OVERFLOW
(RXG)
3 RX_LS_OK
(G)
2 TX_LS_OK
(G)
1 LS_PLL_LOCK
(RXG)
0 HS_PLL_LOCK
(RXG)
Table 7-38. CHANNEL_STATUS_1 Field Description
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Reset
0
1
0
1
Description
Test Pattern status for High/Low/Mixed/CRPAT test patterns. Valid in 10G/1GKX modes.
Alignment has not been determined
Alignment has achieved and correct pattern has been received. Any bit errors are reflected in
HS_ERROR_COUNTER register (0x10)
Lane alignment status
Lane alignment is achieved on the LS side
Lane alignment is not achieved on the LS side
Loss of Signal Indicator.
When high, indicates that a loss of signal condition is detected on HS serial receive inputs
Auto zero complete indicator.
When high, indicates auto zero calibration is complete
Adaptive gain control loop lock indicator.
When high, indicates AGC loop is in locked state
Channel synchronization status indicator.
When high, indicates channel synchronization has achieved
For TI use only.
Valid when decoder is enabled and during CRPAT test pattern verification. When high, indicates
decoder received an invalid code word, or a 8b/10b disparity error. In functional mode, number of
DECODE_INVALID errors are reflected in HS_ERROR_COUNTER register (0x10)
Not applicable in 1GKX mode. When high, indicates underflow has occurred in the transmit
datapath (CTC) FIFO.
When high, in 10GKR and 10G modes indicates overflow has occurred in the transmit datapath
(CTC) FIFO.
Not applicable in 1GKX mode. When high, indicates underflow has occurred in the receive
datapath (CTC) FIFO.
In 10GKR and 10G modes, high indicates overflow has occurred in the receive datapath (CTC)
FIFO. In 1G-KX mode, high indicates a FIFO error.
Receive link status indicator from system side. Applicable in 10G mode only When high, indicates
receive link status is achieved on the system side .
Link status indicator from Lane alignment/Link training slave inside TLK10031. When high,
indicates 10G Link align achieved sync and alignment .
LS Serdes PLL lock indicator
When high, indicates LS Serdes PLL achieved lock to the selected incoming REFCLK0/1_P/N
HS Serdes PLL lock indicator
When high, indicates HS Serdes PLL achieved lock to the selected incoming REFCLK0/1_P/N
74
Detailed Description
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