TLK10031 Datasheet, PDF (47/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
MDC
MDIO
0 1 0 1 PA[4:0]
5'h1E
1 0 16'h9000
1
> 32 "1's"
Preamble
Start
Write
Code
PHY
Addr
REG
Addr
Turn
Around
Data
Idle
Figure 7-25. CL22 – Indirect Address Method – Address Write
MDC
MDIO
0 1 0 1 PA[4:0]
5'h1F
10
DATA
1
> 32 "1's"
Preamble
Start
Write
Code
PHY
Addr
REG
Addr
Turn
Around
Data
Idle
Figure 7-26. CL22 - Indirect Address Method – Data Write
Following timing diagrams illustrate an example read transaction to read contents of Register 16’h9000
using indirect addressing in Clause 22.
MDC
MDIO
0 1 0 1 PA[4:0]
5'h1E
1 0 16'h9000
1
> 32 "1's"
Preamble
Start
Write
Code
PHY
Addr
REG
Addr
Turn
Around
Data
Idle
Figure 7-27. CL22 - Indirect Address Method – Address Write
MDC
MDIO
0 1 1 0 PA[4:0]
5'h1F
Z
0 D15 D0 ¹
> 32 "1's"
Preamble
Start
Read
Code
PHY
Addr
REG
Addr
Turn
Around
Data
Idle
Figure 7-28. CL22 - Indirect Address Method – Data Read
7.4.20 Provisionable XAUI Clock Tolerance Compensation
The XAUI interface is defined to allow for separate clock domains on each side of the link. Though the
reference clocks for two devices on a XAUI/KR link have the same specified frequencies, there are slight
differences that, if not compensated for, will lead to over or under run of the FIFOs on the receive/transmit
data paths.
The XAUI CTC block performs the clock domain transition and rate compensation by utilizing a FIFO that
is 32 deep and 40-bits wide. The usable FIFO size in the RX and TX directions is dependent upon the
RX_FIFO_DEPTH and TX_FIFO_DEPTH MDIO fields, respectively. The word format is illustrated in
Figure 7-29.
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