TLK10031 Datasheet, PDF (83/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
7.5.2.31 HS_CH_CONTROL_1 (register = 0x001D) (default = 0x0000) (device address: 0x1E)
Figure 7-71. HS_CH_CONTROL_1 Register
15
14
RESERVED
RW
13
REFCLK_FREQ_S
EL_1
(RX)
RW
12
REFCLK_FRE
Q_SEL_0
(RXG)
RW
11
RX_CTC_BYP
ASS
(RX)
RW
10
TX_CTC_BYPA
SS
(RX)
RW
9
8
RESERVED
RW
7
6
5
4
RESERVED
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
HS_ENC_BYP
ASS
(RXG)
RW
2
HS_DEC_BYP
ASS
(RXG)
RW
1
0
HS_CH_SYNC_HYSTERESIS[1:
0]
(RXG)
RW
Table 7-52. HS_CH_CONTROL_1 Field Descriptions
Bit
15:14
13
Field
RESERVED
REFCLK_FREQ_SEL_1
(RX)
Type
RW
Reset
Description
For TI use only (Default 2’b00)
Input REFCLK frequency selection MSB. When set, HS_PLL_MULT, LS_MPY and
HS/LS TX/RX RATE settings can be set through related control bits specified in
registers 1E.0002, 1E.0003, 1E.0006
0 = HS_PLL_MULT, LS_MPY and HS/LS TX/RX RATE are set automatically
RW
based on input REFCLK frequency as specified in
REFCLK_FREQ_SEL_0(1E.001D bit 12) (Default 1’b0)
12 REFCLK_FREQ_SEL_0
(RXG)
RW
11 RX_CTC_BYPASS
(RX)
RW
10 TX_CTC_BYPASS
(RX)
RW
9:4 RESERVED
RW
3 HS_ENC_BYPASS
(RXG)
RW
2 HS_DEC_BYPASS
(RXG)
RW
1:0 HS_CH_SYNC_HYSTERESIS[1:0]
(RXG)
1 = Set this value if HS_PLL_MULT, LS_MPY and HS/LS TX/RX RATE
values are NOT to be set automatically.
Input REFCLK frequency selection LSB. Applicable when
REFCLK_FREQ_SEL_1(1E.001D bit 13) is set to 0.
0 = Set this value if REFCLK frequency is 156.25 MHz (Default 1’b0)
1 = Set this value if REFCLK frequency is 312.5 MHz
0 = Normal operation. (Default 1’b0)
1 = Disables RX CTC operation.
0 = Normal operation. (Default 1’b0)
1 = Disables TX CTC operation.
For TI use only (Default 4’b0000)
0 = Normal operation. (Default 1’b0)
1 = Disables 8B/10B encoder on HS side.
0 = Normal operation. (Default 1’b0)
1 = Disables 8B/10B decoder on HS side.
Channel synchronization hysteresis control on the HS receive channel.
00 = The channel synchronization, when in the synchronization state,
performs the Ethernet standard specified hysteresis to return to the
unsynchronized state (Default 2’b00)
01 = A single 8b/10b invalid decode error or disparity error causes the
channel synchronization state machine to immediately transition from sync to
RW
unsync
10 = Two adjacent 8b/10b invalid decode errors or disparity errors cause the
channel synchronization state machine to immediately transition from sync to
unsync
11 = Three adjacent 8b/10b invalid decode errors or disparity errors cause
the channel synchronization state machine to immediately transition from
sync to unsync
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Detailed Description
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