TLK10031 Datasheet, PDF (73/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

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TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
7.5.2.16 RESET_CONTROL (register: 0x000E) (default: 0x0000) (device address: 0x1E)
Figure 7-56. RESET_CONTROL Register
15
14
13
12
11
10
RESERVED
R/W
7
6
5
4
3
2
RESERVED
DATAPATH_
RESET
(RXG)
TXFIFO_
RESET
(G)
R/W
R/W
SC ⁽¹⁾
R/W
SC ⁽¹⁾
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1) After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle.
9
8
1
RXFIFO_
RESET
(G)
R/W
SC ⁽¹⁾
0
RESERVED
R/W
Bit Field
15:8 RESERVED
7:4 RESERVED
3 DATAPATH_RESET
(RXG)
2 TXFIFO_RESET
(G)
1 RXFIFO_RESET
(G)
0 RESERVED
Table 7-37. RESET_CONTROL Field Description
Type
R/W
R/W
R/W
SC
R/W
SC
R/W
SC
R/W
Reset
Description
For TI use only. Always reads 0.
For TI use only. (Default 4'b0000)
Channel datapath reset control. Required once the desired functional mode is configured.
0
Normal operation. (Default 1’b0)
1
Resets channel logic excluding MDIO registers. (Resets both Tx and Rx datapath)
Transmit FIFO reset control. Applicable in 10G mode only. Not required in 10GKR mode as
10GKR FIFO is self centering.
0
Normal operation. (Default 1’b0)
1
Resets transmit datapath FIFO.
Receive FIFO reset control. Applicable in 10G mode only. Not required in 10GKR mode as
10GKR FIFO is self centering.
0
Normal operation. (Default 1’b0)
1
Resets receive datapath FIFO.
For TI use only. (Default 1'b0)
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