TLK10031 Datasheet, PDF (108/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
www.ti.com
7.5.3.30 KR_VS_CTC_ERR_CODE_LN3 (register = 0x8008) (default = 0x0080)
(device address: 0x01)
Figure 7-117. KR_VS_CTC_ERR_CODE_LN3 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
KR_CTC_ERR_CODE_LN3
(R)
RESERVED
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-99. KR_VS_CTC_ERR_CODE_LN3 Field Descriptions
Bit Name
15:7 KR_CTC_ERR_CODE_LN3
(R)
6:0 RESERVED
Type
RW
Reset
RW
Description
Applicable in 10G-KR mode only. XGMII code to be transmitted in case of error
condition. This applies to both TX and RX data paths. The msb is the control bit;
remaining 8 bits constitute the error code. The default value for lane 3 corresponds to
8’h01 with the control bit being 1’b0. The default values for lanes 0~3 correspond to
||LF||
For TI use only. Always reads 0.
7.5.3.31 KR_VS_LN0_EOP_ERROR_COUNTER (register = 0x8010) (default = 0xFFFD) (device address:
0x01)
Figure 7-118. KR_VS_LN0_EOP_ERROR_COUNTER Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
KR_LN0_EOP_ERR_COUNT
(R)
COR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-100. KR_VS_LN0_EOP_ERROR_COUNTER Field Descriptions
Bit Name
15:0 KR_LN0_EOP_ERR_COUNT
(R)
Type
COR
Reset
Description
Lane 0 End of packet Error counter.
End of packet error is detected when Terminate character is in lane 0 and 1 or both of the
following holds:
● Terminate character is not followed by /K/ characters in lanes 1, 2 & 3
● The column following the terminate column is neither ||K|| nor ||A||.
Counter value cleared to 16’h0000 when read.
7.5.3.32 KR_VS_LN1_EOP_ERROR_COUNTER (register = 0x8011) (default = 0xFFFD) (device address:
0x01)
Figure 7-119. KR_VS_LN1_EOP_ERROR_COUNTER Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
KR_LN1_EOP_ERR_COUNT
(R)
COR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-101. KR_VS_LN1_EOP_ERROR_COUNTER Field Descriptions
Bit Name
15:0 KR_LN1_EOP_ERR_COUNT
(R)
Type
COR
Reset
Description
Lane 1 End of packet Error counter.
End of packet error is detected when Terminate character is in lane 1 and one or both of
the following holds:
● Terminate character is not followed by /K/ characters in lanes 1, 2 & 3
● The column following the terminate column is neither ||K|| nor ||A||.
Counter value cleared to 16’h0000 when read.
108 Detailed Description
Submit Documentation Feedback
Product Folder Links: TLK10031
Copyright © 2015, Texas Instruments Incorporated