TLK10031 Datasheet, PDF (86/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
www.ti.com
7.5.2.37 DST_ON_CHAR_CONTROL (register = 0x802A) (default = 0x02FD)
(device address: 0x1E)
Figure 7-77. DST_ON_CHAR_CONTROL Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
DST_ON_CHAR[9:0]
(XG)
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
15:10
9:0
Field
RESERVED
DST_ON_CHAR[9:0]
(XG)
Table 7-58. DST_ON_CHAR_CONTROL Field Descriptions
Type
RW
RW
Reset
Description
For TI use only. Always reads 0.
Applicable only in 1GKX and 10G modes. 10 bit data pattern to trigger ON condition if matched
on transmit side (Default 10’h2FD)
7.5.2.38 DST_OFF_CHAR_CONTROL (register = 0x802B ) (default = 0x02FD)
(device address: 0x1E)
Figure 7-78. DST_OFF_CHAR_CONTROL Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
DST_OFF_CHAR[9:0] (XG)
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
15:10
9:0
Field
RESERVED
DST_OFF_CHAR[9:0]
(XG)
Table 7-59. DST_OFF_CHAR_CONTROL Field Descriptions
Type
RW
RW
Reset
Description
For TI use only. Always reads 0.
Applicable only in 1GKX and 10G modes. 10 bit data pattern to trigger OFF condition if
matched on transmit side (Default 10’h2FD)
7.5.2.39 DST_STUFF_CHAR_CONTROL (register = 0x802C) (default = 0x0207)
(device address: 0x1E)
Figure 7-79. DST_STUFF_CHAR_CONTROL Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
DST_STUFF_CHAR[9:0]
(G)
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
15:10
9:0
Table 7-60. DST_STUFF_CHAR_CONTROL Field Descriptions
Field
RESERVED
DST_STUFF_CHAR[9:0]
(G)
Type
RW
RW
Reset
Description
For TI use only. Always reads 0.
Applicable only in 10G mode. 10 bit data pattern to stuff the output of data switch on transmit
side (Default 10’h207)
86
Detailed Description
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