TLK10031 Datasheet, PDF (48/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
39
data_ln3_in[8:0]
data_ln2_in[8:0]
data_ln1_in[8:0]
0
data_ln0_in[8:0]
www.ti.com
Figure 7-29. XAUI CTC FIFO Word Format
The XAUI CTC performs one of the following operations to compensate the clock rate difference:
1. Delete Idle column from the data stream
2. Delete Sequence column from the data stream (enabled via MDIO)
3. Insert Idle column to the data stream.
The following rules apply for insertion/removal:
• Idle insertion/deletion occurs in groups of 4 idle characters (i.e., in columns)
• Idle characters are added following Idle or Sequence ordered_set
• Idle characters are not added while data is being received
• When deleting Idle characters, minimum IPG of 5 characters is maintained. /T/ characters are counted
towards IPG.
• The first Idle column after /T/ is never deleted
• Sequence ordered_sets are deleted only when two consecutive Sequence columns are received. In
this case, only one of the two Sequence columns will be deleted.
7.4.20.1 Insertion:
When the FIFO fill level is at or below LOW watermark (insertion is triggered), the XAUI CTC needs to
insert an IDLE column. It does so by skipping a read from the FIFO and inserting IDLE column to the data
stream. It continues the insertion until the FIFO fill level is above the mid point. This occurs on the read
side of the FIFO.
7.4.20.2 Removal:
When the FIFO fill level is at or above HIGH watermark (deletion is triggered), the XAUI CTC needs to
remove an IDLE column. It does so by skipping a write to the FIFO and discarding the IDLE column or
Sequence ordered_set. It continues the deletion until the FIFO fill level is below the mid point. This occurs
on the write side of the FIFO.
On the write side of the XAUI CTC FIFO a 40-bit write is performed at every cycle of the 312.5 MHz clock
except during removal when it discards the IDLE or sequence ordered_set. On the read side of the XAUI
CTC FIFO a 40-bit read is performed at every cycle of the 312.5 MHz clock except during insertion when it
generates IDLE columns to the output while not reading the FIFO at all.
In IEEE 802.3-2008 the XAUI clock rate tolerance is given as 3.125 GHz ± 100 ppm, the XGMII clock rate
tolerance is given as 156.25 MHz ± 0.02% (which is equivalent to 200ppm), and the Jumbo packet size is
9600 bytes which is equivalent to 2400 cycles of 312.5 MHz clock. The average inter-frame gap is 12
bytes (3 columns), which implies that there is one opportunity to insert/delete a column in between every
packet on average. This gives one column deletion/insertion in every 2400 columns which results in a 400
ppm tolerance capability. If the IPG increases, then more clock rate variance or larger packet size can be
supported. Note that the maximum frequency tolerance is limited by the frequency accuracy requirement
of the reference clock.
48
Detailed Description
Submit Documentation Feedback
Product Folder Links: TLK10031
Copyright © 2015, Texas Instruments Incorporated