TLK10031 Datasheet, PDF (56/146 Pages) Texas Instruments – TLK10031 Single-Channel XAUI/10GBASE-KR Transceiver

TLK10031
SLLSEL3A – JULY 2015 – REVISED AUGUST 2015
www.ti.com
7.5.2.1 GLOBAL_CONTROL_1 (register: 0x0000) (default: 0x0610) (device address: 0x1E)
Figure 7-41. GLOBAL_CONTROL_1 Register
15
GLOBAL_RESET
(RXG)
R/W
14
13
12
PRTAD0_PIN_EN_SEL[2:0]
(RXG)
R/W
11
RESERVED
R/W
10
9
8
RESERVED
R/W
7
6
5
4
3
2
1
0
RESERVED
PRTAD0_
PIN_EN
(RXG)
PRBS_PASS_OVERLAY[4:0]
(RXG)
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-12. GLOBAL_CONTROL_1 Field Description
Bit Field
15 GLOBAL_RESET
(RXG)
14:12 PRTAD0_PIN_EN_SEL[2:0]
(RXG)
11 Reserved
(RXG)
10:7 RESERVED
6 RESERVED
5 PRTAD0_PIN_EN
(RXG)
4:0 PRBS_PASS_OVERLAY[4:0]
(RXG)
Type
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
(1)_{Global reset.}
0 = Normal operation (Default 1’b0)
1 = Resets TX and RX data path including MDIO registers. Equivalent to asserting
RESET_N.
PRTAD0 pin selection control. Valid only when 1E.0000 bit 5 is 1. PRTAD0 is used for the
assignment specified below
000 = Stopwatch (Default 3’b000)
001 = Reserved
010 = Tx data switch
011 = Rx data switch
100 = Reserved
101 = Reserved
11x = Reserved
Reserved
For TI use only. Always reads 0.
For TI use only (Default 5’b1100)
For TI use only. Always reads 0.
PRTAD0 pin enable control.
0 = Input pin (PRTAD0) is used for the assignment specified in 1E.0000 bits 14:12 (Default
1’b0)
1 = Input pin (PRTAD0) is not used for the assignment specified in 1E.0000 bits 14:12
PRBS_PASS pin status selection. Applicable only when PRBS test pattern verification is
enabled on HS side or LS side. PRBS_PASS pin reflects PRBS verification status on
HS/LS side. LS Serdes lanes 1/2/3 are not applicable in 1GKX modes.
1xx00 = PRBS_PASS reflects HS serdes PRBS verification. If PRBS verification fails on HS
serdes, PRBS_PASS will be asserted low. (Default 5’b10000)
00000 = Status from HS Serdes side
00001 = Reserved
000x1 = Reserved
00100 = Status from LS Serdes side Lane 0
00101 = Status from LS Serdes side Lane 1
00110 = Status from LS Serdes side Lane 2
00111 = Status from LS Serdes side Lane 3
01000 = Reserved
01001 = Reserved
0101x = Reserved
01100 = Reserved
01101 = Reserved
01110 = Reserved
01111 = Reserved
(1) After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle.
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Detailed Description
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